Formal Verification

Job Function Functional Formal Verification Engineer – Lead We are seeking an experienced Functional Formal Verification Engineer to join our team and lead formal verification efforts for complex digital designs. As a Lead Formal Verification Engineer, you will play a critical role in ensuring the quality and reliability of our digital designs. Qualifications: • Bachelor's or Master's degree in Electrical/Electronics Engineering, Computer Engineering, or a related field. • 5+ years of experience in formal verification of complex IP/SubSystem/SoCs, with a strong understanding of digital logic design and verification techniques. • Expertise in formal verification tools and property specification languages (e.g., SVA, PSL), as well as proficiency in HDLs such as System Verilog, Verilog or VHDL. • Experience with industry-standard EDA formal tools. • Experience with scripting languages (e.g., Python, Tcl, Perl) and programming languages such as C/C++/SystemC. • Excellent problem-solving and analytical skills, with the ability to debug complex issues and optimize verification performance. • Strong communication and interpersonal abilities, with experience working in a team environment and collaborating with cross-functional teams. • Proven track record in technical leadership and mentoring, with experience guiding junior engineers and contributing to the development of formal verification methodologies. Responsibilities • Lead complete formal verification for single or multiple design blocks and IPs, including developing and implementing formal verification strategies and test plans. • Create comprehensive formal verification test plans and specifications to ensure thorough coverage of design functionality. • Prove design properties, identify bugs, and collaborate with design teams to improve micro-architectures and ensure design correctness. • Craft innovative solutions for verifying complex design architectures, including developing re-usable and optimized formal models and verification code bases. • Mentor junior team members and provide technical leadership in formal verification methodologies, including training and guidance on industry-standard tools and techniques. • Collaborate with cross-functional teams, including design and verification, to ensure seamless integration of formal verification into the overall verification flow. Preferred Skills: • Experience with CPU, GPU, or other complex digital architectures, including knowledge of industry-standard protocols (e.g., AXI, CHI, PCIe). • Familiarity with UVM methodology and/or other simulation-based verification methodologies. • Experience with advanced FV performance optimization techniques, such as abstraction methods, property decomposition, and other state-space reduction techniques. • Expertise in Jasper or VC Formal products is highly desirable. Job Locations • India: Bangalore