Senior Lead Digital Design
Overview
• The Digital Design Engineer is responsible for defining and realizing Digital functions on IPs, Subsystem or IC level based on required specifications.
• He is responsible for design, verification and evaluation of those. He is accountable for designing according to specifications, quality and reliability needs. Participation in problem solving for Digital and system domain of the device. Author of the design-specific documentation for internal and external use.
• The candidate will work as a design engineer for wireless/communication ASICs development.
• The main responsibilities include IP delivery and silicon validation support.
• The candidate may be working full ASIC design cycle from design, RTL coding, verification, synthesis, timing closure, DFT, backend support and silicon bring-up.
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RISC-V ecosystem
NXP Semiconductors Netherlands B.V. in the RISC-V ecosystem
RISC-V International: Strategic
NXP Semiconductors NV is American Dutch semiconductor manufacturer with dual headquarters in Eindhoven, Netherlands and Austin, Texas.
- NXP is putting RISC-V cores into its mainstream products: a Linux-capable RISC-V core was reported to debut on an NXP i.MX SoC
- Broad MCU/applications-processor vendor tracked in RISC-V market analyses alongside other incumbents
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