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Lead Design Engineer

Cadence Design Systems, Inc.

BANGALORERTL / HDLVerificationPosted Sep 21, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • SystemVerilog
  • UVM
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer. • 4+ years of Design Verification experience with SV/UVM • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. • Design Verification experience verifying complex designs and leading projects from concept to verification closure. • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantage We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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