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Lead Software Engineer

Cadence Design Systems, Inc.

AUSTINPhysical designPosted Oct 17, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • Place and route
  • C
  • C++
  • Python
  • Tcl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. About the Role Join the Innovus team to develop next-generation routing and physical synthesis technologies for digital IC design. You will work on high-performance, multi-threaded systems that enable advanced semiconductor design flows. Key Responsibilities • Research, design, implement, and optimize algorithms for physical synthesis and routing engines. • Develop robust, scalable software in C/C++ on Linux platforms. • Collaborate with global R&D teams and product engineers to deliver innovative solutions. • Debug and resolve complex issues in large-scale distributed systems. Minimum Qualifications • Ph.D. degree or Master’s degree with minimum 2 years of work experience in Computer Engineering or Science, Electrical Engineering, or related field. • Strong programming skills in C/C++ and experience with Linux development. • Solid understanding of data structures, algorithms, and software engineering principles. • Excellent analytical and problem-solving skills. Preferred Qualifications • Knowledge of physical design flows, timing analysis, and routing algorithms. • Experience with multi-threaded programming and performance optimization. • Experience with GPU programming • Familiarity with scripting languages (Tcl, Python) for automation. • Prior exposure to EDA tools or IC design environments. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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