Senior Meshing Developer
SHANGHAIPosted Sep 21, 2026
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Responsibilities
• Design, develop, and optimize advanced meshing algorithms for CAD and simulation workflows.
• Implement and maintain Delaunay-based mesh generation and adaptation techniques.
• Develop efficient methods for mesh coarsening and refinement (e.g., bisection methods).
• Enhance and support surface meshing algorithms, with emphasis on mesh cleaning and robustness.
• Collaborate with geometry and solver teams to ensure seamless integration of meshing technologies.
• Contribute to software architecture, performance optimization, and scalability of meshing workflows.
• Mentor junior developers and provide technical leadership in meshing technology.
Qualifications
• Ph.D. in Computer Science, Applied Mathematics, Computational Engineering, or a related field with 7+ years of experience, OR Master’s degree with 10+ years of experience.
• Proven expertise in Delaunay mesh generation and mesh adaptation techniques.
• Strong experience in mesh coarsening and refinement by bisection methods.
• Proficiency in surface meshing, geometry processing, and mesh cleaning techniques.
• Deep knowledge of C++ (modern standards) and advanced data structures.
• Solid understanding of numerical methods and computational geometry.
• Familiarity with geometric modeling kernels (ACIS preferred) is a strong plus.
• Excellent problem-solving, analytical, and debugging skills.
• Strong communication and teamwork skills.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
More roles at Cadence Design Systems, Inc.
Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Credit & Collections Analyst
Cadence Design Systems, Inc.
SHANGHAIOct 28, 2026Sr Principal Project Manager - AE
Cadence Design Systems, Inc.
SHANGHAIRTL / HDLVerificationSoC / ASICOct 28, 2026IT -Staff Systems Engineer - VM
Cadence Design Systems, Inc.
SHANGHAI 07Oct 28, 2026Software Engineer II: Hardware Job Scheduler R&D
Cadence Design Systems, Inc.
BELO HORIZONTERTL / HDLPhysical designSoC / ASICOct 28, 2026