Senior R&D Service Engineer: IC Design Flow (all genders)

Senior R&D Service Engineer: IC Design Flow (all genders) SAL is looking for an experienced IC-Design Flow Engineer within the Chip Design Team. As such, you will contribute to building, optimizing, and maintaining scalable IC-Design flows from architectural validation through sign-off for advanced ASIC/SoC projects. You will work together both with internal staff as well as external partners and customers to ensure a robust and effective development environment offering a flexible and modular tool chain that can be easily adapted to different technologies, EDA Vendors and applications. Your future tasks include: • Ownership of projects design set-up by configuring and initializing end-to-end EDA environments, managing tool licenses, and ensuring seamless integration across multiple PDKs and technology nodes. • Improvements of existing flow methodologies and creation of new ones, utilization of version-controlled repositories to guarantee reproducibility, auditability, and smooth cross-team collaboration. • Definition of automation scripts and CI/CD pipelines that streamline synthesis, DFT, verification, and physical implementation processes. • Providing hands-on technical guidance and troubleshooting support to design and verification teams on EDA tool usage, performance tuning, and debugging. • Identifying bottlenecks and inefficiencies in existing workflows, proposing and implementing scalable solutions to reduce time-to-tapeout and improve productivity. • Managing PDK integration, EDA tool upgrades, and license optimization while ensuring strict compliance with foundry requirements and internal quality standards. • Maintaining robust, well-documented flow configurations and script libraries, enabling rapid onboarding and consistent project execution. • Overseeing flow validation across benchmark and production projects, ensuring accuracy, repeatability, and alignment with milestone targets. • Supporting cross-site as well as partner & customers engineering teams, fostering a culture of continuous improvement and technical excellence. Your profile: • A master’s degree in Electrical Engineering, Computer Engineering, Physics, or a closely related field. • A solid technical understanding of digital/analog IC development methodologies, combined with hands-on experience with major EDA platforms (Synopsys, Cadence, Siemens/Mentor, etc.). • At least 3 years’ industrial experience as an IC Design Flow Engineer or in a similar role supporting multi-site ASIC/SoC design teams. • Proficiency in scripting and automation (Python, Tcl, Perl, Bash) and familiarity with version control and CI/CD systems (Git, Jenkins, etc.). • A structured working approach, a proactive mindset, and strong problem-solving skills. • The ability to quickly understand complex technical aspects related to EDA Flow and suggest improvements. • Excellent command of English, spoken and written; German is a plus. Important Facts about SAL: • Diverse research activities with many technical challenges. • State-of-the-art laboratory facilities and equipment. • Location in the heart of Europe in Austria – relocation support for non-European nationalities. • Internal and external training opportunities for career development. • Family & children friendly - actively shaping the compatibility of family and career. • “Vital4SAL” to promote a healthy workplace (e.g. SAL coaching pool, trainings on mental health, physical activities, healthy snacks, 24/7 accident insurance) • € 4 per day meal allowance in restaurants or € 2 per working day in supermarkets. • Public transport initiative (subsidy for the “Klimaticket”) • Our values: Open door policy, flexibility in working hours, casual dress code, diverse teams, working with people of different nationalities, informal communication, lifelong learning, compatibility of family and career, sustainability, personal growth, and collective advancement. This position is subject to the Collective Agreement for employees in non-university research (Research CA) starting in occupational group E (E1 salary = EUR 4.381, paid 14 times a year) based on 38,5 hours per week). For this position we offer competitive salaries and additional benefits based on your experience and qualifications, starting with a minimum gross salary of EUR 62.000 (annual, based on an All-out contract). About us: Silicon Austria Labs (SAL) is a top research center for Electronics and Software Based Systems (ESBS). At three locations (Graz, Villach, Linz), SAL is conducting research along the entire ESBS value chain in the areas of sensor systems, power electronics, intelligent wireless systems, microsystems and embedded systems to develop future-oriented solutions for industrial production, health, energy, mobility, safety and more. SAL brings together key players from industry, science and research and thus valuable expertise and know-how and conducts cooperative, application-oriented research along the value chain. Cooperative projects are co-financed by SAL and enable a fast and unbureaucratic project start. SAL is thus shaping the high-tech location Austria and Europe and developing the future. Innovation is our top priority and so are our employees. We are a family-friendly company and support the compatibility of work and family as much as possible. That is why we have been awarded the Work and Family Certificate until 2026. But we are constantly working on new measures to offer our employees an environment where they feel good, healthy and motivated. Editorially recommended external content Show VideoI agree that external content is displayed to me. This means that personal data is transmitted to third-party platforms. Silicon Austria Labs has no influence on this. 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