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Sr Principal Product Validation Engineer

Cadence Design Systems, Inc.

BEIJINGPosted Sep 21, 2026
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Skills named in this posting

  • Mixed-signal
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Position Description: Plan and develop strategy to test/qualify SPICE simulators Work closely with team to enhance product quality and customer support. Build tools and setup test method to improve test process/coverage. Position Requirements: MS in Microelectronics, EE, or relevant. MS with 10+ or Dr. with 6+ year IC relative work experience. Familiar with Cadence Virtuoso Design Environment and Analog/Mixed-Signal Circuit Simulation. Good at communication and team leading. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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