← Back to roles

Sr Principal Design Engineer

Cadence Design Systems, Inc.

BANGALORERTL / HDLVerificationPosted Sep 21, 2026
Apply on Cadence Design Systems, Inc.

Overview

Cadence Design Systems, Inc.
Open roles
678
At this company
See all
Similar roles
156
Same title, 18 companies
Search
Added in 30 days
678
At this company, still open

Skills named in this posting

  • SystemVerilog
  • UVM
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. • BE/BTech/ME/MTech - Electrical / Electronics / VLSI with an experience as a design and verification engineer • 12+ years of Design Verification experience with SV/UVM • Strong background on functional verification fundamentals, environment planning, test plan generation, environment development is a must. • Design Verification experience verifying complex designs and leading projects from concept to verification closure. • Strong hands-on UVM and System Verilog coding experience and functional verification environment development is required. Prior experience in IP verification of memory IP (DDR/HBM/GDDR) would be an added advantag We’re doing work that matters. Help us solve what others can’t.

Apply on the employer's site

Original posting: cadence.wd1.myworkdayjobs.com

Apply on Cadence Design Systems, Inc.

RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

Same employer

More roles at Cadence Design Systems, Inc.

View all 678