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Digital Design Engineer

Owl

RTL / HDLVerificationPhysical designSoC / ASICPosted Oct 2, 2026
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Skills named in this posting

  • SystemVerilog
  • Verilog
  • STA
  • Place and route
Location: Remote | Employment Type: Full Time About the Role Reporting to the Manager of ASIC Engineering, the Digital Design Engineer will design digital circuit solutions based on architecture specifications and will be involved in physical implementation using industry standard synthesis and analysis tools. This role requires effective collaboration with system architect, analog and layout design engineers, and verification engineers to ensure the success of our projects. A critical requirement for this position is the ability to immediately contribute at a high technical level including rapidly assimilating into active programs, assuming ownership of complex design blocks, and delivering results with minimal ramp up time or supervision. What You’ll Accomplish • Generate RTL at module and system level to comply with architecture specifications • Generate and execute constraint driven synthesis and timing closure techniques • Execute back-end tools for timing/power analysis and place and route • Conduct functional analysis, performance analysis (e.g. signal integrity, power, etc.) and interface analysis of digital components and systems. • Conduct comprehensive reviews at various phases of the design process • Adhere to excellent documentation practices to maintain clear and precise records Role Level & Scope • Individual contributor role What We’re Looking For Required • Demonstrated ability to quickly integrate into ongoing ASIC development efforts and independently deliver production quality design results with minimal oversight (high priority requirement) • Experience in digital circuit design of complex ASICs • Experience with design, simulation, and synthesis tools like Cadence and Synopsys • Experience with physical layout, place and route • Proven track record of successful designs going to production • Understanding of semiconductors and ASICs • Experience with GlobalFoundries 22FDX or similar process node • Bachelor degree in Electrical Engineering or Computer Engineering • 5+ years of experience in digital circuit design • 5+ years of experience with industry standard Cadence tools; Virtuoso, Xcelium, Quantus, Innovus, Tempus, Voltus • Familiarity and experience with Cadence tools Spectre and PVS/Pegasus preferred • Proficiency in Verilog and SystemVerilog targeted to ASIC platforms • Strong analytical and problem-solving skills • Strong initiative, proactive work ethic, collaboration and prioritization skills • Strong verbal and written communication skills • Comfortable presenting to varied audiences including company executives Compensation Range $130k – $160k annually, based on experience, qualifications, and geographic location, plus applicable benefits. Apply for this role Opens an email to hr@owlai.us with the role title filled in. Attach your CV and tell us briefly why this one.

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Original posting: owlai.us

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