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PhD Position F/M Making Caches Predictable: Bounded Lifetime Monitoring and Management for Real-Time Systems

Inria (French Institute for Research in Computer Science and Automation)

Posted Oct 7, 2026
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Skills named in this posting

  • Cache coherency
  • Performance modeling
  • C
  • C++
  • Python
PhD Position F/M Making Caches Predictable: Bounded Lifetime Monitoring and Management for Real-Time Systems Download job offer in PDF format Contract type : Fixed-term contract Level of qualifications required : Graduate degree or equivalent Fonction : PhD Position About the research centre or Inria department The Inria Centre at Rennes University is one of Inria's nine centres and has more than thirty research teams. The Inria Centre is a major and recognized player in the field of digital sciences. It is at the heart of a rich R&D and innovation ecosystem: highly innovative PMEs, large industrial groups, competitiveness clusters, research and higher education players, laboratories of excellence, technological research institute, etc. Context The PhD will be led by Inria Rennes, in close collaboration with RPTU and Inria Lille under the ANR PRCI CoCoDaLi Additional information about the city and the university Rennes is a vibrant and student-friendly city in northwestern France. The city has a thriving student culture, with plenty of bars, restaurants, cultural events, and an affordable cost of living. Additionally, Rennes is evaluated as one of the best cities to live in Europe. Rennes is home to the University of Rennes, one of the largest universities in France. The University of Rennes has a strong focus on innovation and technology. It is home to many world-renowned research institutes, including INSA, IRISA, and INRIA Rennes. These institutes offer a wide range of Ph.D. programs in computer science, covering various topics such as artificial intelligence, machine learning, data science, and hardware and software engineering. Ph.D. students in Rennes benefit from close relationships with faculty and access to state-of-the-art facilities. The students also have the opportunity to collaborate with leading researchers worldwide. Team’s LinkedIn page: TARAN's LinkedIn Team’s webpage: TARAN Assignment Context Caches are one of the main reasons modern processors are fast — and one of the main reasons real-time systems are hard to certify. In safety-critical domains such as autonomous vehicles, avionics, robotics, industrial control, and cyber-physical systems, software must not only produce the correct result; it must also do so within a guaranteed deadline. To provide such guarantees, engineers need reliable bounds on the Worst-Case Execution Time, WCET, of each task. Yet caches make this difficult: they evict data that will be needed later, and create interference between tasks or even within the same task. Today, much of this interference is treated pessimistically. Timing analyses often assume worst-case cache behavior because they cannot precisely know which cache blocks are hits or misses. This pessimism leads to overestimated WCET bounds, reduced schedulability, underused hardware resources, and more expensive system designs. The goal of this PhD is to design mechanisms that turn caches from a source of unpredictability into a resource that can be controlled, reasoned about, and exploited more efficiently in real-time systems. Main activities Research Activities This PhD focuses on the design, analysis, implementation, and evaluation of predictable cache management mechanisms for real-time systems, with the goal of improving execution efficiency while enabling tighter and more reliable WCET bounds. To achieve that, we will propose low-overhead, bounded, and analyzable mechanisms for monitoring memory block lifetimes and cache management mechanisms to reduce WCET pessimism. We will investigate hardware-assisted and software-assisted mechanisms to monitor the runtime evolution of memory object lifetimes in the cache hierarchy. The monitoring mechanisms must have constant and bounded overhead, independent of the cache state, so that they remain compatible with WCET analysis. We will design runtime cache management mechanisms that enforce allocation and scheduling decisions, at different granularities. We will evaluate these mechanisms in terms of predictability, implementation complexity, compatibility with memory hierarchies and cache coherence protocols, and performance impact. The PhD will include a systematic analysis of the trade-offs between monitoring granularity, management granularity, runtime overhead, WCET pessimism, and system performance. The research will bridge offline scheduling, cache allocation, and runtime enforcement to improve both predictability and efficiency in real-time systems. Skills Candidate Profile The candidate should have a strong background in one or more of the following areas: • computer architecture • cache and memory hierarchy design • real-time systems • operating systems or runtime systems • WCET analysis Good programming skills are expected, preferably in C/C++, and Python. Experience with architectural simulators, such as GEM5, and low-level systems programming would be an advantage. Languages: proficiency in written English and fluency in spoken English. The interviews for the PhD will be in English. Relational skills: the candidate will work in a research team, where regular meetings will be set up. The candidate has to be able to present the progress of their work in a clear and detailed manner. Other values appreciated: Open-mindedness, strong integration skills, and team spirit. Most importantly, we seek highly motivated candidates. Benefits package • Subsidized meals • Partial reimbursement of public transport costs • Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.) • Possibility of teleworking (after 6 months of employment) and flexible organization of working hours • Professional equipment available (videoconferencing, loan of computer equipment, etc.) • Social, cultural and sports events and activities • Access to vocational training Remuneration monthly gross salary 2300 euros Apply for this position Share • Facebook • Linkedin • Twitter • Email General Information • Theme/Domain : Architecture, Languages and Compilation System & Networks (BAP E) • Town/city : Rennes • Inria Center : Centre Inria de l'Université de Rennes • Starting date : 2027-04-01 • Duration of contract : 3 years • Deadline to apply : 2026-12-31 Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed. Instruction to apply Please submit online : your resume, cover letter and letters of recommendation eventually Defence Security : This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment. Recruitment Policy : As part of its diversity policy, all Inria positions are accessible to people with disabilities. Contacts • Inria Team : TARAN • PhD Supervisor : Kritikakou Angeliki / angeliki.kritikakou@irisa.fr About Inria Inria, the French national institute for research in digital science and technology, supports the French government in national research and innovation strategies in the digital field, acting as Digital Programs Agency. Inria leads over 300 research and innovation projects with its 3,500 scientists, engineers, and support staff, in partnership with universities and the digital ecosystem (businesses, entrepreneurs, and public stakeholders). Together, we explore strategic fields such as artificial intelligence, cybersecurity, quantum computing, cloud technologies, digital transformation in healthcare, digital twins, and digital technologies for defence. We develop practical solutions such as software, tech startups, partnerships with national companies, and cutting-edge training programmes. Our goal is to drive scientific, technological, and industrial excellence to ensure France’s digital sovereignty.

RISC-V ecosystem

Inria (French Institute for Research in Computer Science and Automation) in the RISC-V ecosystem

RISC-V International: Community

The French Institute for Research in Computer Science and Automation (French: Institut national de recherche en informatique et en automatique) is a French national research institution focusing on computer science and applied mathematics.

  • RISC-V security research: mentorship projects implementing RISC-V ISA extensions for control-flow and data-flow integrity
  • Microarchitecture-security research relevant to RISC-V CPUs

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