Lead Product Validation Engineer
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- SystemVerilog
- VHDL
- UVM
- Python
- Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Cadence Advantage
The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success
Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.
We are looking for experienced IP / SoC Verification Engineers with strong hands-on exposure to join our product validation team.
Key Responsibilities:
• Testbench development, test creation, and execution
• Debugging simulation failures and protocol issues
• Functional, code, and assertion coverage closure
• Collaboration with design, architecture, and validation teams
• Support regression, reviews, and verification sign-off
•
Mandatory Skills:
• 4-6 years of experience in IP / SoC Verification
• Strong hands-on experience with SystemVerilog & UVM
• Experience with one or more high-speed protocols:
• Good understanding of SoC fundamentals
• Strong debugging and problem-solving skills
• Hands on experience VHDL Design.
• Scripting skills ( Python / Perl / Shell)
EDUCATION:
• MS in Electrical/Electronics/Computer Engineering with 4+ year experience or BE/BTech in Electrical/Computer/Electronics Engineering.
Behavioral skills required:
• Must possess strong written, verbal and presentation skills.
• Good communication and interpersonal skills, demonstrate teamwork and collaboration skills.
• Ability to establish a close working relationship with both customer peers and management.
• Explore what’s possible to get the job done, including creative use of unconventional solutions
• Work effectively across functions and geographies
• Push to raise the bar while always operating with integrity
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
More roles at Cadence Design Systems, Inc.
Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Credit & Collections Analyst
Cadence Design Systems, Inc.
SHANGHAIOct 28, 2026Sr Principal Project Manager - AE
Cadence Design Systems, Inc.
SHANGHAIRTL / HDLVerificationSoC / ASICOct 28, 2026IT -Staff Systems Engineer - VM
Cadence Design Systems, Inc.
SHANGHAI 07Oct 28, 2026Software Engineer II: Hardware Job Scheduler R&D
Cadence Design Systems, Inc.
BELO HORIZONTERTL / HDLPhysical designSoC / ASICOct 28, 2026