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Chip Design Verification Engineer

NVIDIA Corporation

Israel, Tel AvivRTL / HDLVerificationPosted Aug 30, 2026
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Skills named in this posting

  • SystemVerilog
  • UVM
We are now looking for a best-in-class Chip Design Verification Engineer to join our outstanding GPU-Networking Silicon Engineering team. As a DV Engineer at NVIDIA's GPU-Networking group, you'll make a real impact in a dynamic, technology-focused company while being a part of the team that develops the flagship product of todays’ semiconductor industry – NVIDIA’s GPU Super-Chip. What you’ll be doing: • Work in a DV (Design Verification) team that has a global responsibility over deliverable units and clusters to the silicon GPU • Integrations and Full-Chip models • Verification of chip blocks/entities according to specifications under challenging constraints • Your daily work will involve all aspects of Design Verification : Planning, Coding, Coverage and Integration What we need to see: • 3+ years of experience in RTL design verification. • B.Sc. in Electrical Engineering or Computer Engineering. • A team player with good communication and interpersonal skills. Ways to stand out from the crowd: • Background in Specman and System-Verilog UVM • Knowledge in Networking NVIDIA has some of the most forward-thinking and hardworking people in the world working for us. Are you a creative and autonomous engineer who loves a challenge? Come join our team and help us build the future HPC and data centers. NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer.

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Original posting: jobs.nvidia.com

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RISC-V ecosystem

NVIDIA Corporation in the RISC-V ecosystem

RISC-V International: Premier Board

Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.

  • NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
  • Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
  • Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage

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