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Lead Software Engineer

Cadence Design Systems, Inc.

SAN JOSEPosted Oct 20, 2026
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Skills named in this posting

  • Mixed-signal
  • C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. You will be a member of an expert R&D team creating technologies and products that enable static and dynamic transistor level analysis and characterization of the most advanced custom digital and mixed-signal circuits You work will be focused on: - Research and development of AI/ML technology to bring order of magnitude speed/capacity/usability improvements to design analysis and characterization of digital and analog circuits - Development of tools / infrastructure for characterization data mining - Modeling designs effects dominant in advanced technology nodes such as aging and variation Desired Skills and Experience: - Industry experience developing and maintaining C++ based applications on a Unix or Linux environment - Experience with quality and software processes -Experience in transistor level circuit design is a strong plus - Experience in the use of AI/ML for EDA is a strong plus. - Proficiency designing data structures, algorithms, and software engineering principles The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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