Principal Product Engineer (Analog Design Automation)
SAN JOSEPosted Oct 21, 2026
Overview
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for a Product Engineer to drive the development and customer adoption of Virtuoso AI‑driven Layout Automation flows.This is a customer‑facing role that sits at the intersection of analog layout expertise, automation technology, and customer workflows, and plays a critical role in scaling next‑generation Virtuoso automation flows.We are looking for highly motivated and self‑driven engineers with:
• Strong hands‑on experience with analog / mixed‑signal layout
• Deep familiarity with the Virtuoso Custom Design Platform
• Exposure to layout automation, migration, or constraint‑driven flows
• Proven ability to work directly with customers, understand use‑cases, and articulate technical concepts clearly
• Scripting experience is a plus
• BS/MS degree in Electrical/Computer Engineering (or related degree) with at least 5 years of relevant experience
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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