Datacenter Compute Accelerator Architect

Role Summary We are seeking a highly specialized Datacenter Compute Accelerator Architect to lead the design and integration of dedicated hardware accelerators within our next-generation DC silicon. As datacenter workloads increasingly rely on heterogeneous computing, offloading critical functions (such as cryptography, data compression, networking, and memory movement) from the main CPU/compute cores is vital for maximizing system-level performance and efficiency. In this role, you will define the architecture of these on-chip uncore accelerators and ensure they integrate seamlessly with the coherent interconnect, memory hierarchy, and hypervisor software stack. You will work at the intersection of hardware and software to deliver scalable, high-throughput, and low-latency acceleration solutions for hyper-scale cloud environments. Key Responsibilities • Architecture Definition: Define the microarchitecture and write detailed specifications for tightly-coupled uncore accelerators (e.g., Crypto/Security, Compression/Decompression, DMA engines, Tensor cores, Data Analytics offloads). • SoC Integration: Integrate accelerator blocks into the coherent interconnect (e.g., AMBA CHI, proprietary NoC) and memory subsystem. Manage data flows to ensure optimal latency and bandwidth utilization without starving CPU cores. • HW/SW Co-Design: Partner closely with kernel and driver engineers to define software programming models, APIs, and descriptor formats. • Virtualization & Security: Ensure accelerators support cloud-native environments by implementing robust virtualization (e.g., SR-IOV, PASID) and integrating with memory management units (SMMU/IOMMU) for secure, isolated execution. • PPA & Performance Trade-offs: Conduct rigorous Power, Performance, and Area (PPA) analysis. Work with performance modeling teams to simulate accelerator throughput and latency under heavy datacenter workloads. • Execution Leadership: Serve as the technical focal point during RTL implementation, verification, and silicon bring-up, ensuring the final silicon matches architectural intent. #LI-JK1