DFT Intern - 2027
Overview
- Added in 30 days
- 647
- At this company, still open
Skills named in this posting
- Verilog
- Perl
DFT focus on strategy definition through logic design and insertion, pre-silicon verification, pattern generation, and ATE bringup for NVIDIA chips, with special emphasis on ATE bringup, pattern/generation and validation, yield debug, failure analysis and volume diagnosis for ramp to production.
As a DFT intern at NVIDIA, you will help own the testing methodology from strategy definition through logic design and insertion, pre-silicon verification, pattern generation, and ATE bringup.
What you’ll be doing:
• DFT logic implementation and verification
• Maintain DFT flow and run regression
• Run DFT verification
• Pattern generation and bringup
What we need to see:
• Strong logic design and verification background
• Possess very basic knowledge of DFT
• Skilled in Perl/tcl programming
• Proficient at Verilog HDL
• Pursuing MS/PhD in EE
Ways to stand out from the crowd:
• Prefer to have experience with logic simulators and debug tools (such as vcs, ncsim, verdi)
• Familiar with C/C , Makefile is a plus
• Strong problem solving and analytical skills
• Excellent communication skills and teamwork
NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. If you're creative and autonomous, we want to hear from you!
Apply on the employer's site
Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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