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Sr Principal Design Engineer

Cadence Design Systems, Inc.

BANGALOREPosted Sep 21, 2026
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Senior Principal Engineer SI/PI: Candidate will own and Lead HBM PHY SI/PI design. Candidate shall make technical decisions improving quality and schedule of program. Candidate would coordinate SI/PI deliverables. Candidate shall organize and conduct thorough project gate design reviews. Candidate will review HBM PHY customer Interposer and Package designs. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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