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Technical Director, Digital Design Methodology & Flow Architecture

NXP Semiconductors Netherlands B.V.

Austin (Oakhill, Office)RTL / HDLPhysical designFull timePosted Sep 20, 2026
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Skills named in this posting

  • Place and route
  • Python
  • Tcl
  • Perl
Role Overview The Technical Director, Digital Design Methodology & Flow Architecture will define and deploy a repeatable, traceable, and customizable end-to-end digital design flow for advanced process technologies. The role combines RTL-to-GDS implementation expertise, static verification, PPA optimization, AI tool enablement, and hands-on agentic flow development. Key Responsibilities • Architect a modular RTL-to-GDS flow supporting synthesis, place and route, timing/power closure, static verification, signoff, and GDS delivery. • Enable agentic execution, AI-assisted debugging, design-space exploration, and automated analysis loops for EDA workflows. • Establish repeatable and traceable flow practices, including standard recipes, configuration baselines, metrics, dashboards, audit trails, regression checks, and release management. • Deploy flows for new process technologies in partnership with design, CAD/methodology, foundry, and EDA vendor teams. • Improve productivity, turnaround time, quality-of-results, and PPA through automation, methodology tuning, and scalable reuse. Education and Experience Level • Education: B.S. in Electrical Engineering, Computer Engineering, Computer Science, or related field required; M.S. or Ph.D. preferred. • Level: Director of Technology-level technical leader of digital design, CAD/methodology, EDA implementation, or flow architecture experience. • Scope: Proven ability to set technical direction, influence senior stakeholders, and lead cross-functional flow transformation across functional domains or technology nodes. Required Experience and Skills • Deep hands-on experience in end-to-end digital implementation, RTL-to-GDS, static design and timing analysis, formal/static verification, signoff, ECO, and PPA closure. • Strong expertise in synthesis, floorplanning, place and route, clock-tree synthesis, power optimization, congestion analysis, and advanced-node implementation challenges. • Hands-on agentic AI workflow development experience, including task planning, tool invocation, result interpretation, retry logic, human-in-the-loop checkpoints, and autonomous execution patterns. • Practical MCP experience, including MCP clients/servers, tool and resource exposure, secure access, JSON-RPC-style communication, and integration with engineering systems. • Strong scripting and automation skills using Tcl, Python, Perl, shell, or equivalent flow automation technologies. • Experience with major EDA ecosystems such as Synopsys, Cadence, Siemens EDA, or equivalent internal platforms. • Ability to translate design challenges into repeatable methodology improvements, reusable automation, and measurable productivity gains. • Experience defining and executing deployment and migration strategies from current script-driven digital design flows to goal-driven agentic flows, including phased rollout, MCP/tool-adapter integration, validation against golden flows, human-in-the-loop checkpoints, observability, governance, rollback planning, and production adoption across RTL-to-GDS workflows. Preferred Qualifications • Experience with AI-enabled EDA, agent orchestration, retrieval-augmented generation, multi-agent workflows, and workflow state management. • Experience developing MCP-enabled connectors or tool adapters for EDA tools, job schedulers, dashboards, repositories, databases, or compute environments. • Experience building production-quality flows with observability, auditability, permission control, evaluation harnesses, regression validation, documentation, and release management. More information about NXP in the United States... NXP is an Equal Opportunity/Affirmative Action Employer regardless of age, color, national origin, race, religion, creed, gender, sex, sexual orientation, gender identity and/or expression, marital status, status as a disabled veteran and/or veteran of the Vietnam Era or any other characteristic protected by federal, state or local law. In addition, NXP will provide reasonable accommodations for otherwise qualified disabled individuals. #LI-97b2

RISC-V ecosystem

NXP Semiconductors Netherlands B.V. in the RISC-V ecosystem

RISC-V International: Strategic

NXP Semiconductors NV is American Dutch semiconductor manufacturer with dual headquarters in Eindhoven, Netherlands and Austin, Texas.

  • NXP is putting RISC-V cores into its mainstream products: a Linux-capable RISC-V core was reported to debut on an NXP i.MX SoC
  • Broad MCU/applications-processor vendor tracked in RISC-V market analyses alongside other incumbents

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