Lead Design Engineer
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Assembly
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
This position requires the development of optimized audio codecs and audio processing applications for Tensilica's configurable embedded HiFi series of processors.
● Developing and Optimizing performance of audio processing firmware using C level changes using C instrinsics.
● Updating the audio firmware for features, interfaces and new processor configurations.
● Documenting the implementation for engineering details and for customers.
● Interacting with internal customer engineering team & partners and resolving different Audio issues.
Required Skills
• The candidate should have a good experience in developing and optimizing DSP applications in C and assembly language for a DSP or DSP-like processor, and should have a good grasp of the issues surrounding software performance tuning.
• The candidate should have experience applying principles of good software and interface design and should have experience with at least one version control system.
• Good technical communication skills are required.
• Candidate must be self-motivated and capable of working independently or as part of a team. Experience with embedded hardware and knowledge of computer system architecture is desirable.
• In-depth knowledge of audio/speech processing and standards (e.g., MPEG, Dolby, DTS, G.7xx, etc.) is essential.
• 5+ years relevant work experience in DSP in audio and speech signal processing.
• Educational qualification: BE/BS in CS or EE is required, MTech/MS is preferred.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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