Product Engineer II - Verification
Overview
- Added in 30 days
- 677
- At this company, still open
Skills named in this posting
- UVM
- Emulation
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
- Work closely with the Sales team to identify and scope opportunities for the Cadence Verification Division’s products.
- Plan, execute and manage key technical evaluations and benchmark with existing and potential customers.
- Train, ramp-up and accompany customer project.
- Conduct basic and advanced trainings, presentations and demos as necessary.
- Providing technical expertise to address clients’ queries, which need expert involvement.
- Aligned closely with corporate engineering and sales/marketing team on customer requirement for product direction/improvement
- The candidate should possess minimum BS level of CS or EE with 3+ years of industry experience
- Minimum 3+ years experiences in Verification/Prototyping and consumer application design/debugging by EDA solution.
- Hands-on experience on SOC Emulation/Acceleration, Hybrid solution, UVM, Verification IPs or Transactors a big plus
- Familiar with Simulator (IES, VCS, etc) and some experiences of emulator/accelerators (PXP, Zebu, Veloce).
- Knowledge of Linux and tcl is a must
- Good program/engagement management skill
- Effective team player and good relationship with co-workers, willing to learn
- Good communication skills in English and a strong desire for working in a global environment with customers and BU people
- Current passport is required with no travel limitations
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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