Analog/Mixed-Signal Design Verification Engineer/Lead

• Work in AMS IP Design Verification, in UVM-based verification environment. • Work in DV process from specification to test plan, to configurable test bench, drivers and checkers development, to test suite building to meet functional and code coverage goals • Act as Technical Lead of a Design Verification group/team by providing technical guidance, planning schedule and resource to meet requirement for project deliverables, fostering methodology advancement, and so on. • Apply wide range of Digital and/or AMS DV skills to help and support AMS IP or Chip DV Teams to establish or enhance new or existing DV capabilities, including but not limited to developing scalable and portable Test bench, test cases, drivers, checkers, assertions and reference models, and running RTL and Gate Level simulations and reaching all coverage closures. • Communicate and collaborate with global architecture, design, verification, and post-Silicon testing teams to address new needs or requirement on DV Support. • Contribute to continuous improving on AMS DV process for better quality and efficiency through methodology and process improvements.