software engineering intern
BEIJINGPosted Sep 21, 2026
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- C++
- Python
- PyTorch / TensorFlow
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are looking for an EDA engineer intern for our spectre FX (FastSPICE ) circuit simulator to research and develop new technology for speeding up large scale transistor level post-layout circuit
Position Requirements:
- EE, CS, physics or math major PhD or master's degree.
- Skilled in C, C++ or python, pytorch.
- SPICE simulator or digital circuit simulator development experience is a plus.
- AI related project and experience is a plus.
- Fast learner, highly motivated with good communication skills to solve technical problems.
- Circuit design experience is a plus.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
More roles at Cadence Design Systems, Inc.
Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Credit & Collections Analyst
Cadence Design Systems, Inc.
SHANGHAIOct 28, 2026Sr Principal Project Manager - AE
Cadence Design Systems, Inc.
SHANGHAIRTL / HDLVerificationSoC / ASICOct 28, 2026IT -Staff Systems Engineer - VM
Cadence Design Systems, Inc.
SHANGHAI 07Oct 28, 2026Software Engineer II: Hardware Job Scheduler R&D
Cadence Design Systems, Inc.
BELO HORIZONTERTL / HDLPhysical designSoC / ASICOct 28, 2026