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Lead Product Validation Engineer

Cadence Design Systems, Inc.

SHANGHAIPosted Sep 21, 2026
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Skills named in this posting

  • Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Responsibilities: • Work within a global multi-functional team to review SI/PI/EM analysis technologies, project plans and functional specifications, develop test criteria and write test plans, manually exercise and test functionality of the Sigrity products • Develop automated tests within the existing test environment • Maintain comprehensive regression suites for monitoring products quality • Work with the team to solve customer issues Requirements • BS degree or MS degree in Electrical Engineering, Computer Science, Applied Mathematics or similar • 4+ year SI/PI/EM related working experience • Experience in using Sigrity tools or other simulation tools • Understand test processes and methodologies in a software development environment • Good understanding of power integrity and signal integrity and EM technology • Basic knowledge of IC design including knowledge of passive components such as inductors, capacitors and transformers • Be familiar with Linux system, and scripting skills with TCL, Perl, Shell, Matlab is a plus • Knowledge of PCB design, routing, and packaging is a plus • Having good analytical and problem-solving skills is essential • Strong written and verbal communication skills, in English and Chinese are mandatory • Self-starter, self-sufficient, able to work independently as well as with teams, able to multitask We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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