Principal / Senior GPU SW Performance Engineer — Post‑Training
Overview
- Added in 30 days
- 482
- At this company, still open
Skills named in this posting
- C++
- Python
- PyTorch / TensorFlow
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
Drive the performance of post‑training workloads on AMD Instinct™ GPUs. You’ll work across kernels, distributed training, and framework integrations to deliver fast, stable, and reproducible training pipelines on ROCm.
THE PERSON:
The ideal candidate is passionate about software engineering and the craft of training performance. You lead sophisticated cross‑stack issues—spanning data loaders, kernels, distributed training, and compilers—to clear resolution. You communicate crisply and collaborate effectively with framework, compiler, kernel, and model teams across AMD, driving measurable improvements with rigor, ownership, and reproducibility.
KEY RESPONSIBILITIES:
• Lead performance for finetuning and RL training solutions on AMD GPUs.
• Improve throughput, memory efficiency, and stability across data, model, and optimizer steps.
• Optimize multi‑GPU/multi‑node training and communication patterns.
• Contribute efficient kernels/ops and targeted graph‑level optimizations.
• Profile, diagnose, and resolve bottlenecks using standard tooling; prevent regressions in CI.
• Ship reproducible pipelines and documentation adopted by internal teams and external developers.
• Collaborate with framework, compiler, and model teams to land durable improvements.
•
PREFERRED EXPERIENCE:
• Proven GPU performance engineering for deep learning (ROCm/HIP, Triton, or similar).
• Hands‑on with SFT. LoRA and RL‑based training at scale.
• Strong PyTorch experience (torch.distributed, FSDP/ZeRO or equivalent).
• Proficient in Python and C++; comfortable reading/writing kernels when needed.
• Experience with distributed systems and collective communication libraries.
• Track record of turning profiles into fixes, upstreaming changes, and documenting results.
ACADEMIC CREDENTIALS:
• B.S./M.S./Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
LOCATION:
San Jose, CA preferred. Other US based locations may be considered.
#LI-MV1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
Drive the performance of post‑training workloads on AMD Instinct™ GPUs. You’ll work across kernels, distributed training, and framework integrations to deliver fast, stable, and reproducible training pipelines on ROCm.
THE PERSON:
The ideal candidate is passionate about software engineering and the craft of training performance. You lead sophisticated cross‑stack issues—spanning data loaders, kernels, distributed training, and compilers—to clear resolution. You communicate crisply and collaborate effectively with framework, compiler, kernel, and model teams across AMD, driving measurable improvements with rigor, ownership, and reproducibility.
KEY RESPONSIBILITIES:
• Lead performance for finetuning and RL training solutions on AMD GPUs.
• Improve throughput, memory efficiency, and stability across data, model, and optimizer steps.
• Optimize multi‑GPU/multi‑node training and communication patterns.
• Contribute efficient kernels/ops and targeted graph‑level optimizations.
• Profile, diagnose, and resolve bottlenecks using standard tooling; prevent regressions in CI.
• Ship reproducible pipelines and documentation adopted by internal teams and external developers.
• Collaborate with framework, compiler, and model teams to land durable improvements.
•
PREFERRED EXPERIENCE:
• Proven GPU performance engineering for deep learning (ROCm/HIP, Triton, or similar).
• Hands‑on with SFT. LoRA and RL‑based training at scale.
• Strong PyTorch experience (torch.distributed, FSDP/ZeRO or equivalent).
• Proficient in Python and C++; comfortable reading/writing kernels when needed.
• Experience with distributed systems and collective communication libraries.
• Track record of turning profiles into fixes, upstreaming changes, and documenting results.
ACADEMIC CREDENTIALS:
• B.S./M.S./Ph.D. in Computer Science, Computer Engineering, Electrical Engineering, or equivalent
LOCATION:
San Jose, CA preferred. Other US based locations may be considered.
#LI-MV1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Apply on the employer's site
Original posting: careers.amd.com
RISC-V ecosystem
Advanced Micro Devices (AMD) in the RISC-V ecosystem
RISC-V International: Strategic
For more than 45 years AMD has driven innovation in high-performance computing, graphics, and visualization technologies; the building blocks for gaming, immersive platforms, and the data center.
- Ships MicroBlaze V, a RISC-V soft-processor core for AMD FPGAs/adaptive SoCs (docs, Vitis quick-start guide, BSP macros)
- amd.com states AMD has been a RISC-V member since 2020
- ROCm/LLVM docs include a RISC-V code-generation target; RISC-V debug support in AMD tools
Same employer
More roles at Advanced Micro Devices (AMD)
Staff Silicon Design Engineer
Advanced Micro Devices (AMD)
Belgrade, SerbiaRTL / HDLVerificationFPGAOct 28, 2026Packaging Engineer
Advanced Micro Devices (AMD)
Hsinchu, TaiwanOct 28, 2026OSAT Execution Program Manager
Advanced Micro Devices (AMD)
Hsinchu, TaiwanOct 28, 2026Senior Staff Silicon Design Engineer - SerDes Validation
Advanced Micro Devices (AMD)
Singapore, SingaporeFirmwareOct 28, 2026RTL Design Engineer - PCIe
Advanced Micro Devices (AMD)
Hyderabad, IndiaRTL / HDLVerificationFirmwareOct 28, 2026Lead Software Development Engineer - NVMe/ VirtIO/SCSI/FCP/ iSCSI/RDMA or TCP
Advanced Micro Devices (AMD)
Bangalore, IndiaKernel / LinuxSoC / ASICOct 28, 2026