RTL2GDS Principal AE
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Formal verification
- STA
- Place and route
- Python
- Tcl
- Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
The Principal Application Engineer will serve as a senior technical leader within Cadence’s North America Field Applications Team, driving strategic customer engagements and influencing next-generation EDA & Agentic-AI solutions. This role demands exceptional technical depth, proven leadership, and the ability to align cross-functional teams toward delivering advanced design solutions for leading semiconductor companies.
Key Responsibilities
• Strategic Leadership: Define and execute technical engagement strategies for top semiconductor design team, ensuring alignment with corporate objectives and customer success metrics.
• Customer Advocacy: Act as a trusted advisor for executive-level stakeholders, guiding adoption of Cadence’s digital implementation, signoff technologies and AgenticAI features across advanced nodes (3nm and below).
• Cross-Functional Collaboration: Partner with R&D and Product Engineering to influence tool enhancements based on real-world customer requirements.
• Innovation & Enablement: Drive complex benchmarks, flow optimizations, and deployment of cutting-edge methodologies for front-end technologies like Synthesis, RTL power estimation, Formal Verification P&R, STA, IR Drop, and power/timing closure.
• Thought Leadership: Represent Cadence at industry forums, author technical papers, and deliver keynote presentations to position Cadence as a market leader.
• Operational Excellence: Establish best practices for engagement models, resource planning, and technical escalations to ensure timely and successful project execution.
• Requirements
• 8+ years of experience in IC design implementation, with demonstrated success in managing large-scale technical programs.
• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• Deep expertise in digital design fundamentals, advanced node implementation (3nm and below), and EDA tool ecosystems.
• Proven track record of leading technical teams and driving customer success at executive levels.
• Strong proficiency in scripting (Tcl, Python, Perl) and flow customization for design closure.
• Excellent communication, negotiation, and leadership skills with the ability to influence internal and external stakeholders.
• Prior experience with Cadence tools (Genus, Innovus, Conformal, Cerebrus) and competitive solutions highly desirable.
The annual salary range for California is $127,400 to $236,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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