DFT Integration Lead

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SMTS DFT Design Engineer THE ROLE: · As a member of the S3 SoC DFx Team, the successful candidate will own/lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. · Position includes DFT design development, data analysis and silicon debug of DFT in leading process technologies. · Strong self-driving ability, should have excellent communication skills (both written and oral) · Strong problem-solving skills KEY RESPONSIBILITIES: · Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT design · Design and develop correct by construction DFT design and support DFT verification · Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. PREFERRED EXPERIENCE: · Experience and an understanding of ASIC DFT, synthesis, simulation and verification flow · Experience is End-to-End DFT flow development/creation. · Expert in Perl, Python, TCL, and ability to create complex flows/scripts. · Strong EDA tools experience (Tessent, Design Compiler, Spyglass,) · Experience in DFT architecture for complex chips · Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration · Proficient in doing basic unit-level verification using simulations. · Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. · Must have experience with integration of various IPs into complex SOCs. · Exposure to Static timing analysis & Timing closure is required. · Scan/ATPG patterns & test flows development, debug, test, and characterization · Excellent hands-on debug skills and scripting skills are critical. · Must have good communication skills and the ability to work in a worldwide team environment. · Knowledge & experience of low power concepts, clock gating, power gating is a plus · Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: · B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering · 11+ years’ experience in DFT Design #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. SMTS DFT Design Engineer THE ROLE: · As a member of the S3 SoC DFx Team, the successful candidate will own/lead the DFT Design and Integration of cutting edge DFT structures including SCAN, ATPG, MBIST, BSCAN. · Position includes DFT design development, data analysis and silicon debug of DFT in leading process technologies. · Strong self-driving ability, should have excellent communication skills (both written and oral) · Strong problem-solving skills KEY RESPONSIBILITIES: · Working closely with the DFT Architecture and the various IP Design teams to align on the DFT requirements and successfully implementing the DFT design · Design and develop correct by construction DFT design and support DFT verification · Working closely with the RTL designers, Verification Engineers, and PD team to find creative ways to accelerate the identification of functional defects. PREFERRED EXPERIENCE: · Experience and an understanding of ASIC DFT, synthesis, simulation and verification flow · Experience is End-to-End DFT flow development/creation. · Expert in Perl, Python, TCL, and ability to create complex flows/scripts. · Strong EDA tools experience (Tessent, Design Compiler, Spyglass,) · Experience in DFT architecture for complex chips · Experience in RTL development using Verilog/System Verilog having worked on RTL for IP and SoC integration · Proficient in doing basic unit-level verification using simulations. · Experience with RTL quality check tools/methodologies such as Spyglass, CDC, Lint is required. · Must have experience with integration of various IPs into complex SOCs. · Exposure to Static timing analysis & Timing closure is required. · Scan/ATPG patterns & test flows development, debug, test, and characterization · Excellent hands-on debug skills and scripting skills are critical. · Must have good communication skills and the ability to work in a worldwide team environment. · Knowledge & experience of low power concepts, clock gating, power gating is a plus · Experience with post-silicon bring up is a plus ACADEMIC CREDENTIALS: · B.E/B.Tech/M.E/M.Tech in Electrical/Electronics Engineering · 11+ years’ experience in DFT Design #LI-RR1 Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.