Senior Mask Layout Design Engineer
Overview
- Added in 30 days
- 647
- At this company, still open
Skills named in this posting
- Mixed-signal
- Python
Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity? We are looking for a Senior Mask Layout Design Engineer – someone who is excited to join a growing group of diverse individuals responsible for handling high-speed mixed-signal circuit designs!
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 fueled the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can pursue, and that matter to the world. This is our life’s work, to amplify human creativity and intelligence. Join our dynamic team today!
What you'll be doing:
• The role entails working collaboratively and multi-functionally with a multi-disciplinary team of Circuit designers and mask designers.
• Perform physical layout for digital and mixed-signal functions like clock generators, op-amps, sensors, security circuits, power delivery circuits in state-of-the-art sub-micron CMOS technologies using Cadence tools
• You'll work with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
• Job duties will include floor planning, custom layout and verifying against design rules and schematics.
• Fill, post-processing, DRC mitigation, and foundry interactions
What we need to see:
• BS in Electrical Engineering (or equivalent experience)
• At least 7+ years of hands-on layout design experience
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies. Validated experience with Cadence custom circuit design tools - particularly virtuoso
• Experience running and debugging DRC and LVS with verification tools such as Dracula, Hercules, Calibre
• Leadership experience mentoring and assisting junior mask designers, implementing standard processes for the team, and keeping checklists for optimal layout design.
• Communicate with diverse team of mask designers across geographies and timezones.
• Ability to work optimally in a team, good interpersonal skills and positive energy.
• Proficiency in scripting languages like perl, python, skill etc. is a plus.
• Knowledge of layout automation is a definite plus.
NVIDIA is a pioneer in bringing groundbreaking technology to new markets. We have some of the most forward-thinking and hardworking people in the world working with us. If you're creative and autonomous, we want to hear from you!
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until January 26, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Apply on the employer's site
Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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