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Software Architect

Cadence Design Systems, Inc.

SHANGHAIRTL / HDLVerificationPosted Sep 21, 2026
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Skills named in this posting

  • SystemVerilog
  • Verilog
  • AMBA / AXI
  • C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job responsibilities: • Responsible for designing, developing, for updating, maintaining, documenting and supporting IP models of standard AMBA protocols and proprietary CUP protocol for use on hardware based verification products. • Work closely with customer to adopt and develop new features and spec version on new proprietary CUP protocol. • Interface with internal teams (AE, PE, VIP and ABVIP), and external customer (Mainly Xiaomi) to work on diverse problems and solutions related to emulation, simulation, or verification. • Perform as team member toward cross verification of and cross training in AMBA IP as well as in developing and using lifecycle processes to ensure product quality. Job Requirements: • The position requires BSEE, or equivalent, with a minimum of 4 years of industry experience in designing hardware and software systems. • Must have excellent communication skills with both written and spoken English. • C / C++ knowledge and hands-on experience. • RTL design knowledge using Verilog/SystemVerilog is required along with experience using RTL verification tools and flows. • Debugging experience. • Experience with team-wide collaboration tools and process. • Drive and ability to schedule workload and plan own tasks effectively. Preferred: • Verification experience using Cadence simulation and/or emulation products is highly desired. • Experience in AMBA protocols is highly desired . CHI knowledge / experience is strongly recommended and is a big advantage. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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