Principal Engineer, Project Management - Chip Power
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NVIDIA Switches ASIC group is seeking a top-tier ASIC Power technical manager to lead the development of our next-generation ASICs Power execution, modelling, and optimization. Join us in shaping the future of technology! As an ASIC Power Project Lead, you will manage the pre-silicon Power activities of NVIDIA's most advanced and complex switch ASICs. You will collaborate with a cross-disciplinary team, interacting with unit-level ASIC, Physical Design, CAD, Package Design, Firmware & Software, DFT, System Design, Analog Design, and other specialized teams.
What you’ll be doing:
• Lead the ASIC Power execution from architecture stages until tape-out.
• Post-Silicon Power Activities: Monitor and support chip Power from power-on and bring-up, quality phases, to mass production.
• Power Execution Plans: Define and implement Power execution plans in collaboration with cross-discipline leaders.
What we need to see:
• BS or MS in Computer or Electrical Engineering or equivalent experience.
• 15+ overall years of proven experience in chip design.
• 8+ years of experience in VLSI / chip design, leading teams of at least 8 direct reports.
• High system view with ability to collaborate with multiple interfaces.
• Strong analytical and problem-solving skills.
• Excellent communication and teamwork abilities.
• Experience in ASIC power optimization, ASIC power modelling, thermal, reliability, Power Integrity, Package and Board design is a plus.
If you are creative, autonomous, and love a challenge, we want to hear from you! Join NVIDIA and be a part of the team that is driving the future of technology.
Apply on the employer's site
Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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