Design Engineer I
CARYRTL / HDLPhysical designSoC / ASICPosted Oct 13, 2026
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Emulation
- DFT
- Python
- Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We are a small group of individuals designing among the most complex chip in the world getting into the award-winning Cadence Design Systems Palladium platform…
As such we are seeking an experienced DFT engineer which role will span across the full spectrum of the DFT implementation: from architecture definition through silicon testing and debug.
A bonus, this individual will have cross functional teams’ interactions not only within our group; but across Cadence and the multiple BU involved in our developments.
Key responsibilities:
• Define and implement SoC level DFT architecture for large and complex designs.
• Develop, integrate, and support SCAN, ATPG, MBIST, BSCAN and iJTAG.
• Perform DFT insertion, verification, and coverage analysis at block and SoC levels.
• Drive pre-silicon DFT sign-off, including DRC closure and coverage targets.
• Support post-silicon debug, failure analysis and yield learning.
• Collaborate with RTL, verification, physical design and operation teams.
Qualifications:
• BS degree
• At least 3 years of hands-on experience in SoC DFT.
Must-have skills:
• Strong expertise in SCAN, ATPG, MBIST.
• Experience with pre-silicon validation and post-silicon debug.
• Strong problem solving and debugging skills.
• Ability to work effectively in a cross-functional engineering environment.
Good-to-have skills:
• Scripting experience (TCL, Perl, Python or equivalent) for flow automation and analysis.
• Experience with IP-level DFT integration and reuse.
• Exposure to low-power DFT considerations and complex clocking architectures.
• Familiarity with manufacturing test flows and silicon yield improvement.
The annual salary range for California is $88,900 to $165,100. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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