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Senior/Staff Engineer, Technical Manager (Design Verification)

MediaTek Inc

SingaporeRTL / HDLVerificationPosted Dec 12, 2023
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Overview

MediaTek Inc
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Skills named in this posting

  • SystemVerilog
  • Verilog
  • UVM
  • Formal verification
Develop and review test plans Develop verification environment/testbench in Module/IP/SOC level Develop verification IP and reference model Implement test with randomization based coverage driven verification methodology Implement functional and functional/code coverage closure Hands-on code/debug with UVM, SystemVerilog, Verilog and SystemC: Low Power verification Formal verification #LI-WC1

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Original posting: careers.mediatek.com

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RISC-V ecosystem

MediaTek Inc in the RISC-V ecosystem

RISC-V International: Strategic

We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.

  • Named in coverage of RISE, the Linux Foundation Europe RISC-V Software Ecosystem project, and RISC-V edge-AI market analysis
  • Listed on the landscape as a RISC-V International member

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