Block Verification Technical Lead

You will own the verification of one key block of our coherent AI system, leading a team of 3–4 engineers, to tape-out sign-off. Your scope covers the system router, the fabric that carries requests and data between the cores, memory and the rest of the chip. Here the challenge is traffic: every request must reach the right place, in the right order, without deadlock, even when all cores push at full speed. About Semidynamics Semidynamics builds memory-centric AI inference silicon in Barcelona. Our chips combine RISC-V CPUs, Vector and Tensor Units and our Gazzillion Misses™ memory engine, so that large language models are never starved of data. In April 2026, SK hynix, one of the world's leading memory makers, made a strategic investment in the company. You will not inherit a mature flow at a company of 10,000 people. You will shape it, with a team you lead and a design team one desk away. What you will do Own the verification of your block • Maintain the block verification plan, aligned with the overall strategy set by the Verification Lead. • Maintain, run and update the block testbench in UVM: agents, reference model, scoreboards, functional coverage and assertions. • Drive the block to sign-off: coverage closure, bug trends. Lead your team • Lead a team of 3–4 verification engineers: split the work, review testbenches and tests, unblock people. • Mentor your engineers, make decisions. • Keep your regressions and CI healthy, and push automation. Work with design and the other leads • Review and understand the block microarchitecture with the RTL designers. • Review the interface contracts with the neighbouring blocks: what your block assumes, and who checks it. • Deliver agents, checkers and coverage that the other teams reuse at system level. • Report status and risks clearly to the Verification Lead. Why this role is different • Hands-on and leader at once. You still write testbenches and debug failures, decide the next scenario to implement, while you grow a team around you. • A block you really own. You know it better than anyone, down to the last corner case, and your sign-off decides if it is ready. • The RTL authors are next to you. You can challenge a microarchitecture choice at the whiteboard, before it becomes a bug. • A clear next step. Leading a block team is the natural path towards leading verification for a whole system. What you bring Must have • 6+ years of hands-on design verification, with at least one block taken to tape-out. • Expert SystemVerilog and UVM: you have architected a block testbench from scratch, including the reference model and scoreboards. • Strong functional coverage and assertion-based verification (SVA). • Technical leadership: you have written a verification plan, driven coverage closure and guided other engineers. • Deep knowledge of at least one of: cache controllers, coherent interconnects, or CPU cores. • Working knowledge of SoC bus protocols: AXI, CHI. • Experience with a major simulator and debugger (Questa, VCS or Xcelium; Visualizer or Verdi). • Scripting (Python, Bash) and experience running regressions. • B.Sc. or M.Sc. in Electrical or Computer Engineering, or equivalent experience. • Fluent English. Nice to have • RISC-V, CPU cluster or AI accelerator verification. • Cache coherence protocols (CHI, ACE, MESI/MOESI) and memory ordering. • CI infrastructure (GitLab). • First experience managing people. How you work • You always ask: "Who/what actually checks this?" • You keep inventing new scenarios to find the next bug before it finds us. • You like to mentor, and you enjoy seeing engineers on your team grow. Why Semidynamics • Work at one of Europe's most promising deep-tech semiconductor scale-ups, from silicon to systems. • Office in Barcelona city centre: 4 days on site, 1 day from home. • 1 week per year to work from anywhere in the world. • Competitive package. • A collaborative, technical culture that values direct ownership and clear thinking. • Barcelona itself: the sea, the mountains and a strong engineering community nearby.