Custom SOC ASIC Engineer - New College Grad 2027
Overview
- Added in 30 days
- 658
- At this company, still open
Skills named in this posting
- SystemVerilog
- Verilog
- UVM
- AMBA / AXI
- C
- C++
- Python
- Perl
NVIDIA NVLink™ Fusion delivers industry-leading AI scale-up and scale-out performance with NVIDIA technology plus semi-custom ASICs or CPUs . NVIDIA is hiring a Custom Silicon Design Engineer to design, analyze, and evolve next generation NVLINK Fusion product. We are looking for special individuals with passion and desire to deliver innovative products. Together, we will build the next generation of life changing SoC's. If you are a motivated individual that understands how SoC systems are architected and built, has intimate knowledge of client requirements, and understands various development cycles, this is your place to be.
What you’ll be doing:
• Functional and IO IP development
• Different IPs integration and release for custom silicon
• Build SOC or sub-system, signoff function/performance and QoR
• Methodology improvement for high-efficiency custom silicon development
What we need to see:
• Masters degree in EE/CS or related field
• Basic C/C++ knowledge is a must
• Scripting knowledge (Perl/Python/Shell)
• Basic digital circuit/verilog knowledge is a must
• Basic verification knowledge is a must
Ways to stand out from the crowd:
• Quick learner, willing to take challenges in a new field
• Fluent English and good communication skills
• Familiar with VCS, system Verilog and UVM
• Background with ASIC design flow, like synthesis
• Familiar with AMBA protocols such as AXI, ACE, CHI, ATB, etc.
Apply on the employer's site
Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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