Post-Doctoral Research Visit F/M Reliability Assessment and Fault-Tolerance Methods for Cloud FPGA and PIM Accelerators

Post-Doctoral Research Visit F/M Reliability Assessment and Fault-Tolerance Methods for Cloud FPGA and PIM Accelerators Download job offer in PDF format Contract type : Fixed-term contract Renewable contract : Yes Level of qualifications required : PhD or equivalent Fonction : Post-Doctoral Research Visit About the research centre or Inria department The Inria center at the University of Rennes is one of eight Inria centers and has more than thirty research teams. The Inria center is a major and recognized player in the field of digital sciences. It is at the heart of a rich ecosystem of R&D and innovation, including highly innovative SMEs, large industrial groups, competitiveness clusters, research and higher education institutions, centers of excellence, and technological research institutes. Context Context and Motivation The TARAN research group at INRIA/IRISA in Rennes, France, invites applications for a postdoctoral researcher in the area of reliability assessment and fault tolerance for modern hardware accelerators. The position is part of ongoing European, international, and national research projects conducted with academic and industrial partners. The postdoctoral researcher will focus on accelerator platforms that are relevant for Cloud deployment, particularly FPGA-based accelerators and processing-in-memory (PIM). Specialized accelerators are increasingly adopted in Cloud infrastructures to execute compute- and data-intensive workloads efficiently [1]. FPGA accelerators offer reconfigurability and high performance per watt, while PIM computing architectures aim to reduce the cost of data movement by placing computation close to memory [2]. These platforms are especially relevant for workloads with substantial memory traffic, including artificial intelligence, data analytics, and signal-processing applications. Despite this potential, relatively few studies have investigated the reliability of FPGA accelerators in a Cloud context. Similarly, much of the existing reliability literature on PIM computing concentrates on emerging memory technologies, such as RRAM, STT-MRAM, or PCM, and relies on simulations or simplified prototypes [3, 4]. Such studies provide useful insights but do not fully address the reliability challenges of accelerators that will be deployed in large scale systems. A detailed understanding of fault sources, fault propagation, and application-level effects is therefore needed before these architectures can be used confidently in demanding computing environments. Conventional replication-based solutions, such as duplication or triple modular redundancy, may impose prohibitive performance, area, and energy costs. The project will consequently investigate efficient, targeted fault-tolerance methods grounded in a detailed characterization of accelerator vulnerabilities. Research Scope The postdoctoral researcher will develop and apply a comprehensive methodology for evaluating the reliability of FPGA accelerators and PIM. The work will combine experimental and simulation-based approaches across several abstraction levels. The methodology for validation will use fault-injection campaigns at microarchitectural and software levels. For PIM architectures, the evaluation will use representative benchmark suites, such as PrIM, together with additional workloads selected according to the target architecture. For FPGA accelerators, the work will build on applications developed in the TARAN team national projects, with a particular emphasis on AI workloads. The objective is to characterize fault sensitivity, identify critical hardware and software resources, quantify the propagation of faults to workload-level outcomes, and assess practical mechanisms that improve robustness with limited overhead. The expected outcomes include reliability-evaluation methodologies, fault models and experimental datasets, cross-layer analysis tools, and efficient fault-mitigation strategies for Cloud-oriented FPGA and PIM accelerators. The postdoctoral researcher will work closely with the TARAN team and project partners and will contribute to the development of innovative research proposals and publications in this area. Relevant Team Expertise The team has established experience in reliability assessment, cross-layer reliability analysis, efficient fault-injection methodologies, and selective protection of AI accelerators. This postdoctoral project will extend these strengths toward FPGA-based Cloud accelerators and commercially relevant PIM systems. Selected Team Reference Publications Roquet, F. F. dos Santos, P. Rech, M. Traiola, O. Sentieys and A. Kritikakou, "Cross-Layer Reliability Evaluation and Efficient Hardening of Large Vision Transformers Models," 2024 61st ACM/IEEE Design Automation Conference (DAC) M. Traiola, et al., Impact of High-Level-Synthesis on Reliability of Artificial Neural Network Hardware Accelerators, IEEE Transactions on Nuclear Science, 2024. B. Tonetto, et al., "ENFOR-SA: End-to-end Cross-layer Transient Fault Injector for Efficient and Accurate DNN Reliability Assessment on Systolic Arrays," 2026 IEEE 44th VLSI Test Symposium (VTS) F. d. Santos et al., "Improving Deep Neural Network Reliability via Transient-Fault-Aware Design and Training," in IEEE Transactions on Emerging Topics in Computing, 2025 B. Tonetto, et al. Scalable Reliability Assessment of DNNs through Simultaneous Fault Injection. IEEE/ACM Design Automation Conference, DAC 2026 R. B. Tonetto, et al. The Anatomy of a Misprediction: Tracking Terrestrial and Orbital Radiation-Induced Errors in Systolic Arrays. SC 2026 - International Conference for High Performance Computing, Networking, Storage, and Analysis, Nov 2026, Chicago, United States Other publications from TARAN: https://team.inria.fr/taran/publications/ Other References [1] C. Bobda, et al. The Future of FPGA Acceleration in Datacenters and the Cloud. ACM Trans. Reconfigurable Technol. Syst. 15, 3, Article 34 (September 2022) [2] A. Sebastian, et al. Memory devices and applications for in-memory computing. Nat. Nanotechnol. 15, 529–544 (2020). [3] Z. Yan, et al. On the Reliability of Computing-in-Memory Accelerators for Deep Neural Networks. System Dependability and Analytics. Springer Series in Reliability Engineering. Springer, Cham. [4] J. Jung. Reliable Processing-in-Memory. The University of Texas at Austin, Electrical and Computer Engineering, Thesis (May 2025). Assignment Research Scope The postdoctoral researcher will develop methods and tools to evaluate and improve the reliability of cloud-oriented accelerators, with a focus on FPGA platforms and practical PIM architectures. Possible research directions include: • Reliability evaluation of FPGA accelerators and PIM architectures under representative Cloud workloads. • Characterization of fault sources and vulnerable resources in memory, logic, interconnects, and control structures. • Cross-layer analysis of fault propagation from hardware resources to application-level outcomes. • Simulation-based fault injection at microarchitectural and software levels. • Development of fault models, reliability metrics, and experimental methodologies suitable for commercially relevant accelerators. • Design and assessment of efficient fault-mitigation techniques that avoid the excessive cost of full duplication or triple modular redundancy. • Selective protection, architecture-level mitigation, software-level resilience techniques, and cross-layer fault-tolerance strategies. Both theoretical and experimental contributions are welcome, depending on the candidate's expertise. Main activities Role and Responsibilities This is a research-focused academic position, not an engineering or support role. Expected duties include: • conducting original research and publishing in leading venues • supervising and mentoring PhD students and Master’s interns • participating in European and National research projects, including: • research contributions in collaborative work packages • project reporting and deliverables • contribution to project design and writing for future calls • interaction with industrial and academic partners • presenting results at international conferences and consortium meetings Environment and Funding • Institution: INRIA/IRISA, TARAN team, Rennes, France. • Funding: The position is funded through ongoing European and national research projects. Travel related to project activities and scientific dissemination will be covered according to project and institutional rules. • Collaboration: The researcher will work with international academic and industrial partners involved in accelerator reliability, Cloud computing, and dependable computing systems. • Duration: Up to 24 months, subject to the applicable funding framework and institutional conditions. • Start date: 2026, with flexibility depending on administrative procedures and candidate availability. Applications will be reviewed on a rolling basis until the position is filled. Benefits package • Subsidized meals • Partial reimbursement of public transport costs • Leave: 7 weeks of annual leave + 10 extra days off due to RTT (statutory reduction in working hours) + possibility of exceptional leave (sick children, moving home, etc.) • Possibility of teleworking (after 6 months of employment) and flexible organization of working hours • Professional equipment available (videoconferencing, loan of computer equipment, etc.) • Social, cultural and sports events and activities • Access to vocational training Remuneration monthly gross salary 2927 euros according to diploma and experience Apply for this position Share • Facebook • Linkedin • Twitter • Email General Information • Theme/Domain : Architecture, Languages and Compilation System & Networks (BAP E) • Town/city : Rennes • Inria Center : Centre Inria de l'Université de Rennes • Starting date : 2027-01-01 • Duration of contract : 11 months • Deadline to apply : 2026-12-31 Warning : you must enter your e-mail address in order to save your application to Inria. Applications must be submitted online on the Inria website. Processing of applications sent from other channels is not guaranteed. Instruction to apply Please submit online : your resume, cover letter and letters of recommendation eventually Defence Security : This position is likely to be situated in a restricted area (ZRR), as defined in Decree No. 2011-1425 relating to the protection of national scientific and technical potential (PPST).Authorisation to enter an area is granted by the director of the unit, following a favourable Ministerial decision, as defined in the decree of 3 July 2012 relating to the PPST. An unfavourable Ministerial decision in respect of a position situated in a ZRR would result in the cancellation of the appointment. Recruitment Policy : As part of its diversity policy, all Inria positions are accessible to people with disabilities. Contacts • Inria Team : TARAN • Recruiter : Fernandes Dos Santos Fernando / fernando.fernandes-dos-santos@inria.fr The keys to success Candidate Profile Applicants should have a strong research background in one or more of the following areas: • Computer architecture. • Hardware reliability, fault tolerance, or dependability. • FPGA-based accelerator design • Hardware/software co-design. • Microarchitectural simulation, fault modeling, or fault injection. Experience with international collaboration, research-project participation, and student supervision will be considered strong assets. Application Procedure Applications should include a curriculum vitae with a publication list and contact information for at least two references. Highlight high quality publications that you may have in conferences and journals such as MICRO, HPCA, DAC, DATE, DSN, Trans. Reliability, Trans. Computers, TCAD, etc. About Inria Inria, the French national institute for research in digital science and technology, supports the French government in national research and innovation strategies in the digital field, acting as Digital Programs Agency. Inria leads over 300 research and innovation projects with its 3,500 scientists, engineers, and support staff, in partnership with universities and the digital ecosystem (businesses, entrepreneurs, and public stakeholders). Together, we explore strategic fields such as artificial intelligence, cybersecurity, quantum computing, cloud technologies, digital transformation in healthcare, digital twins, and digital technologies for defence. We develop practical solutions such as software, tech startups, partnerships with national companies, and cutting-edge training programmes. Our goal is to drive scientific, technological, and industrial excellence to ensure France’s digital sovereignty.