Senior Engineer - CPU DV
Overview
Skills named in this posting
- SystemVerilog
- UVM
- Microarchitecture
- Out-of-order cores
- Branch prediction
- Cache coherency
- Arm
- x86
About SiFive
As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.
At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.
Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people's lives; making the world a better place, one processor at a time.
Are you ready?
To learn more about SiFive’s phenomenal success and to see why we have won the GSA’s prestigious Most Respected Private Company Award (for the fourth time!), check out our website and Glassdoor pages.
Job Description:
Role Overview:
We are seeking a highly skilled Senior Verification Engineer with 4+ years of experience or the verification of complex CPU core microarchitecture and should have completed a bachelor's or master's in engineering degree. The candidate will drive DV strategy, architecture validation, and closure for high-performance processors, ensuring functional correctness, performance, and quality at silicon level.
Key Responsibilities
• CPU Core Verification
• Own end-to-end verification of CPU core components (Fetch, Decode, Execute, Memory, Pipeline, Cache, MMU)
• Validate microarchitectural features such as:
• Out-of-order execution
• Branch prediction
• Cache coherency
• Virtual memory & paging
• RAS and Fusa
• Develop test plans from architecture specifications and ensure full coverage closure
• Verification Methodology & Execution
• Lead verification using System Verilog / UVM
Develop:
• Testbenches
• Constrained-random tests
• Scoreboards and checkers
• Coverage models (functional + code)
• Drive regressions and debug complex failures across simulation/emulation platforms
• Architecture & Feature Validation
• Work closely with Architecture & Design teams to:
• Understand ISA behavior (e.g., ARM ISA, RISC-V, or x86)
• Validate corner cases, exceptions, interrupts
• Perform ISA-level validation and compliance testing
Additional Information:
This position requires a successful background and reference checks and satisfactory proof of your right to work in:
India
Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export-controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.
SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.
Apply on the employer's site
Original posting: sifive.wd1.myworkdayjobs.com
RISC-V ecosystem
SiFive in the RISC-V ecosystem
RISC-V International: Premier Board
SiFive is a semiconductor company that delivers scalable processor core IP solutions. | Founded in 2015, SiFive is based in San Mateo, California and specializes in agile hardware design and open source chip platforms.
- SiFive is the original commercial RISC-V core IP company, founded by the RISC-V inventors
- Ships broad RISC-V core families, including the Intelligence series expanded for AI workloads (e.g. running BEVFormer on the early-access Intelligence XM platform)
- Works with software partners to make RISC-V a production target, e.g. collaborating with Red Hat on enterprise Linux for RISC-V
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