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Senior ASIC Verification Engineer - Networking Chip Design

NVIDIA Corporation

China, ShanghaiVerificationSoC / ASICPosted Aug 5, 2026
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We are now looking for Fullchip Verification Enginneer for the Networking Switch Chip Design Group. As a Engineer at NVIDIA's Networking Chip Design Group, you'll join a group of passionate engineers to deliver the next generation state of the art Switch Silicon chips. In this position, you'll make a real impact in a dynamic, technology-focused company while developing the industry's best high-speed communication devices, delivering the highest throughput and lowest latency! What you'll be doing: • Work in a combined design and verification team specializing in Switch Fullchip works • Understand the Switch architecture and build on testplan accordingly • Maintain and optimize Fullchip verification enviornment to meet feature requirements efficiently • Develop Fullchip test suites, maintain regressions, debug failures and sign-off coverages What we need to see: • Electrical Engineering B.Sc. or Computer Engineering B.Sc. graduate with high scores or equivalent experience. • 5+ years of experience in DV relevant works • A team player with good communication and interpersonal skills. • Previous experience in full chip verification enviornment for complex chips – an advantage. NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people in the world working for us. Are you creative and autonomous? Do you love the challenge of crafting the highest performance & lowest power silicon possible? If so, we want to hear from you. Come, join our Switch Silicon design team and help us build the next chip in this exciting and quickly growing field

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Original posting: jobs.nvidia.com

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RISC-V ecosystem

NVIDIA Corporation in the RISC-V ecosystem

RISC-V International: Premier Board

Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.

  • NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
  • Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
  • Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage

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