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Senior Memory Controller Verification Engineer

NVIDIA Corporation

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Skills named in this posting

  • SystemVerilog
  • UVM
  • C
  • C++
  • Python
  • Perl
NVIDIA is seeking hardworking, motivated and creative Senior Verification Engineer for our GPU Memory Subsystem IP verification Team! At NVIDIA, we have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. In this position, you will partner with the design and architecture teams to help make the right implementation choices, craft and implement verification test plans, maintain regressions, close coverage and sign off design or both functional correctness and for meeting performance expectations. This position offers the opportunity to have a real impact on multiple product lines including consumer graphics, self-driving cars, HPC, cloud computing, and AI! What you’ll be doing: • Develop verification infrastructure (testbenches, BFMs, checkers, monitors, randoms) • Come up with, review and drive test plan execution for planned features • Understand the performance requirements of your IP, come up with, review and drive performance testplan for your IP • Ensure code and functional coverage of all the RTL which you will verify. • Work with and enable FPGA and software teams to ensure that software is tested. • Plan for and be involved with post-silicon verification and debug. What we need to see: • BS / MS or equivalent experience. • 6+ years of ASIC verification experience of complex design units displaying good attention to detail, teamwork, problem solving and shown success • Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB). • Background with System Verilog and UVM based methodology for ASIC verification. Ways to stand out from the crowd: • Strong C/C++ programming experience • Prior Design or Verification experience of dynamic memory controllers (ddr{2, 3, 4, 5}, lpddr{2, 3,4,5,6}, HBM, or GDDR) • Strong debugging and problem solving skills. • Scripting knowledge (Python/Perl/shell). • Good interpersonal skills and ability & desire to work as a part of a team. With competitive salaries and a generous benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We welcome you join our team with some of the most hard-working people in the world working together to promote rapid growth. Are you passionate about becoming a part of a best-in-class team supporting the latest in GPU and AI technology? #LI-Hybrid Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5. You will also be eligible for equity and benefits. Applications for this job will be accepted at least until July 27, 2026. This posting is for an existing vacancy. NVIDIA uses AI tools in its recruiting processes. NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

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Original posting: jobs.nvidia.com

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RISC-V ecosystem

NVIDIA Corporation in the RISC-V ecosystem

RISC-V International: Premier Board

Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.

  • NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
  • Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
  • Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage

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