Staff / Sr. Staff GPU Engineer – Shader System RTL Design / Microarchitecture

About MediaTek MediaTek is a global fabless semiconductor company powering nearly two billion connected devices annually with system-on-chip technologies. Its solutions span mobile, connectivity, home entertainment, IoT, automotive, and AI-enabled platforms, including market-leading Wi-Fi technologies. For more information, please visit www.mediatek.com. About the Team With MediaTek’s leadership in SoC design, the MediaTek GPU IP team is committed to developing industry-leading, feature-rich, and highly PPA-competitive graphics IP. Our GPU technology is deployed across flagship and mainstream mobile SoCs and is also a foundational technology for adjacent markets including laptops, IoT, AI, VR/AR, automotive, and custom ASIC applications. The team is expanding and hiring top GPU talent across multiple disciplines, including architecture, microarchitecture, RTL design, software drivers, compiler technology, performance modeling, power optimization, and silicon validation. Positions are available in our San Diego and San Jose offices. Position Overview We are seeking a Staff / Senior Staff GPU Engineer specializing in Shader System RTL Design and Microarchitecture to help define, design, and deliver next-generation GPU IP. The ideal candidate will have strong hands-on experience in GPU shader subsystem microarchitecture, RTL implementation, performance analysis, functional debug, and PPA optimization. You will drive the design and optimization of shader core pipelines, thread/warp/wave scheduling, instruction dispatch and issue, execution pipelines, register files, and operand collection. You will work closely with architecture, compiler, software driver, verification, performance modeling, physical design, and post-silicon teams to deliver high-performance, power-efficient GPU IP for mobile, automotive, laptop, IoT, AI, VR/AR, and ASIC markets. Role and Responsibilities • Define, develop, and own GPU shader subsystem microarchitecture specifications. • Lead RTL design for shader-related blocks, including shader pipelines, instruction issue, operand collection, register files, dependency tracking, and pipeline control. • Collaborate with architecture and compiler teams to translate ISA behavior, API requirements, shader workloads, and performance targets into efficient hardware designs. • Analyze GPU workloads and performance data to improve occupancy, throughput, latency hiding, register pressure, and power efficiency. • Support the full GPU IP lifecycle, including microarchitecture definition, RTL coding, lint/CDC/RDC cleanup, verification support, synthesis, timing closure, tape-out, bring-up, and post-silicon debug. • Partner with verification teams on test plans, coverage, assertions, debug strategies, and directed/random test scenarios.