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Design Engineer II

Cadence Design Systems, Inc.

NOIDARISC-VRTL / HDLVerificationPosted Oct 2, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • SystemVerilog
  • UVM
  • Formal verification
  • Microarchitecture
  • PCIe
  • AMBA / AXI
  • C
  • C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Role Overview: Key Responsibilities: • • Verification Infrastructure: Simulation testbenches in C/C++/RTL and lead the development of reusable UVM environments. • Advanced Verification: Champion the integration of formal verification, and AI-driven coverage analysis. • Cross-Functional Collaboration: Partner with microarchitecture, RTL design, and software teams to align verification plans with ISA requirements. • Required Qualifications: • B.Tech/M.Tech in ECE with • Experience in SystemVerilog/UVM and C/C++ for architectural modeling. • Experience with processor integration (e.g., RISC-V or ARM) and industry-standard protocols like AMBA/PCIe. • Expertise in scripting (Perl, Python, or Tcl) for verification flow automation. • Proven track record in verifying complex pipelines, memory subsystems, or ISA implementations. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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