Lead Product Engineer
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- Place and route
- Low-power design (UPF)
- Python
- Tcl
- Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
High-performance and Power-Critical CPU and/or GPU Implementation and Methodology Engineer
Responsibilities / Skills
· Full-chip and block-level implementation from RTL to Signoff, including place-and-route, timing closure, physical verification, power analysis, and optimization.
• Strong understanding of physical design fundamentals including floorplanning, placement, clock tree synthesis, routing, timing analysis, signal integrity, IR drop, and electromigration.
• Experience with timing closure methodologies for setup, hold, power, and area optimization.
• Familiarity with low-power implementation techniques including UPF/CPF, power gating, multi-voltage designs, clock gating, and leakage optimization.
• Need to be automation savvy and able to develop scripts, utilities, and methodologies to improve productivity and design quality.
• Prior experience in Python, Tcl, Perl, Shell, or other programming/scripting languages is a plus.
• Exposure to machine learning and AI-assisted optimization techniques is a plus.
• Familiarity with industry-standard implementation and signoff tools
• Understanding of advanced technology nodes (5nm and below) and associated challenges including congestion, variability, power integrity, and manufacturability is desirable.
• Strong debugging and problem-solving skills with the ability to analyze complex design issues and drive them to resolution.
• Good communication skills and ability to work effectively with cross-functional teams including architecture, RTL, verification, methodology, and CAD teams.
• Experience with data analytics, design-space exploration, or AI-driven optimization frameworks for improving PPA and productivity is highly desirable.
• Experience in PPA optimization, design convergence, benchmarking, methodology development, and large-scale CPU/GPU implementation is a plus.
The annual salary range for California is $119,000 to $221,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
Same employer
More roles at Cadence Design Systems, Inc.
Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Systems Engineer
Cadence Design Systems, Inc.
SHANGHAICompilersKernel / LinuxOct 28, 2026Sr Credit & Collections Analyst
Cadence Design Systems, Inc.
SHANGHAIOct 28, 2026Sr Principal Project Manager - AE
Cadence Design Systems, Inc.
SHANGHAIRTL / HDLVerificationSoC / ASICOct 28, 2026IT -Staff Systems Engineer - VM
Cadence Design Systems, Inc.
SHANGHAI 07Oct 28, 2026Software Engineer II: Hardware Job Scheduler R&D
Cadence Design Systems, Inc.
BELO HORIZONTERTL / HDLPhysical designSoC / ASICOct 28, 2026