Chip Lead / ASIC Director

WHAT YOU DO AT AMD CHANGES EVERYTHING At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career. THE ROLE: As ASIC Director – Chip Lead in our Product Development team, you will be responsible for providing technical leadership to one or more Adaptive & Embedded Computing Group (AECG) device programs. You will have sign-off responsibility for the technical execution of device programs from conception & planning to release to manufacturing. Your leadership responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog & custom design, design for test & manufacturing, verification, physical design & timing closure, physical verification, tapeout and post-silicon validation & qualification. When a problem does not clearly fall under the banner of one technical team or another it becomes the responsibility of the Chip Lead to bring expertise, experience and diplomacy together to coordinate a solution. THE PERSON: This position requires a wide breadth of understanding of and experience with ASIC design and development. It also requires strong interpersonal skills to resolve issues between highly skilled and experienced engineering colleagues. A successful candidate will work with senior silicon design engineers, architects, and micro-architects from a wide variety of technical teams. The candidate will be attuned to the overall goals and objectives of the program and employ excellent communication and problem-solving skills. KEY RESPONSIBILITIES: • Chip Definition and Feasibility – identify critical tradeoffs and architectural decisions • Advise on Feasibility including early estimates of Schedule, Cost, Size, Power, Floorplan, and identify key implementation decisions • Serve as Engineering’s interface to Technical Marketing; ensuring the product meets customer needs and supports the required functions and usage modes • Define/identify new device specific functionality (with Marketing and Architecture) • When needed, negotiate for a new, new version or new variant of an IP (with the IP/COE Lead) • Be aware of devices and programs throughout the organization; foster engineering re-use • Help resolve issues and guide trade-offs that arise during any phase of the program but especially in Physical Design.Execution The Chip Lead works with one or more Program Managers: The Program Manager tracks that IP and chip development milestones and deliverables are achieved as scheduled. The Chip Lead engages and resolves the problem when some aspect of the program is not meeting its planned objectives. When engineering or marketing initiates a change to the program, the Chip Lead communicates the change and its consequences to all stakeholders. PREFERRED EXPERIENCE: • Experience required in ASIC Development Lifecycle. FPGA technical experience is a huge plus • Experience in a leadership role with a semiconductor company • Master’s or PhD in Electrical Engineering, Computer Engineering, or related technical field • Post-silicon validation experience is a strong asset • Strong understanding of semiconductor industry and products. Experience working with Product Planning and Marketing teams is preferred.PREFERRED ACADEMIC CREDENTIALS: • Bachelor’s or Master’s degree in related discipline preferred LOCATION: San Jose, CA #LI-G11 #LI-HYBRID This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy. THE ROLE: As ASIC Director – Chip Lead in our Product Development team, you will be responsible for providing technical leadership to one or more Adaptive & Embedded Computing Group (AECG) device programs. You will have sign-off responsibility for the technical execution of device programs from conception & planning to release to manufacturing. Your leadership responsibilities will focus on problem solving in all aspects of the device development cycle including architecture, RTL, analog & custom design, design for test & manufacturing, verification, physical design & timing closure, physical verification, tapeout and post-silicon validation & qualification. When a problem does not clearly fall under the banner of one technical team or another it becomes the responsibility of the Chip Lead to bring expertise, experience and diplomacy together to coordinate a solution. THE PERSON: This position requires a wide breadth of understanding of and experience with ASIC design and development. It also requires strong interpersonal skills to resolve issues between highly skilled and experienced engineering colleagues. A successful candidate will work with senior silicon design engineers, architects, and micro-architects from a wide variety of technical teams. The candidate will be attuned to the overall goals and objectives of the program and employ excellent communication and problem-solving skills. KEY RESPONSIBILITIES: • Chip Definition and Feasibility – identify critical tradeoffs and architectural decisions • Advise on Feasibility including early estimates of Schedule, Cost, Size, Power, Floorplan, and identify key implementation decisions • Serve as Engineering’s interface to Technical Marketing; ensuring the product meets customer needs and supports the required functions and usage modes • Define/identify new device specific functionality (with Marketing and Architecture) • When needed, negotiate for a new, new version or new variant of an IP (with the IP/COE Lead) • Be aware of devices and programs throughout the organization; foster engineering re-use • Help resolve issues and guide trade-offs that arise during any phase of the program but especially in Physical Design.Execution The Chip Lead works with one or more Program Managers: The Program Manager tracks that IP and chip development milestones and deliverables are achieved as scheduled. The Chip Lead engages and resolves the problem when some aspect of the program is not meeting its planned objectives. When engineering or marketing initiates a change to the program, the Chip Lead communicates the change and its consequences to all stakeholders. PREFERRED EXPERIENCE: • Experience required in ASIC Development Lifecycle. FPGA technical experience is a huge plus • Experience in a leadership role with a semiconductor company • Master’s or PhD in Electrical Engineering, Computer Engineering, or related technical field • Post-silicon validation experience is a strong asset • Strong understanding of semiconductor industry and products. Experience working with Product Planning and Marketing teams is preferred.PREFERRED ACADEMIC CREDENTIALS: • Bachelor’s or Master’s degree in related discipline preferred LOCATION: San Jose, CA #LI-G11 #LI-HYBRID This role is not eligible for visa sponsorship. Benefits offered are described: AMD benefits at a glance. AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here. This posting is for an existing vacancy.