ATE Test Engineer
US, CA, Santa ClaraPosted Aug 28, 2026
Overview
- Added in 30 days
- 658
- At this company, still open
Skills named in this posting
- C++
- Python
- Perl
As one of the technology industry's most desirable employers, NVIDIA is an industry leader in high-performance computing, gaming and AI. NVIDIA's GPUs are extraordinary in performance and efficiency, and we are continually innovating in creative ways to deliver outstanding solutions in a wide range of sectors.
This is a Test Engineer position supporting the Integrated Circuit Defect Analysis (FA) team. The engineer will enable tailored test equipment and software for the Advantest PS5000 and the Teradyne UltraFLEXPlus (UF+) platforms, while working closely with the product TE team and be embedded in the FA team. You will bridge the gap between design, automated test equipment (ATE), and IC failure analysis. You are responsible for co-developing specialized test equipment, adapting FA methodologies, and crafting test scripts that enable diagnostics and root-cause isolation on advanced, high-performance silicon.
What you’ll be doing:
• Port and develop test vectors, patterns, and software on the Advantest V93000 system, specifically the PS5000 module, as well as Teradyne UltraFLEXplus platforms.
• Convert design simulation data (e.g., VCD, EVCD, STIL) into functional, scan, and structural test patterns to recreate IC failures on the tester.
• Partner with FA engineers, design teams, and test floor technicians to translate physical FA steps like ATE-assisted EMMI or OBIRCH into reproducible, electrical test flows.
• Improve turnaround time from device failure to root cause by optimizing tester hardware bandwidth, signal integrity, and diagnostic software flows.
• Design, prototype, and validate custom test hardware (e.g., specialized load boards, probe cards, and device-under-test (DUT) interfaces) for FA setups.
What we need to see:
• B.S. or M.S. in Electrical Engineering, Computer Engineering, or a related technical field, or equivalent experience.
• 5+ years of hands-on experience with Advantest V93000 (PS5000) (SmarTEST 8 environment) and Teradyne UltraFLEXplus (IG-XL software).
• Proficiency with script automation (Python, C++, or Perl) and digital vector processing/debug.
• Familiarity with IC FA flows, failure isolation, electrical fault localization, and yield analysis.
With highly competitive salaries and a comprehensive benefits package, NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and hardworking people on the planet working for us. If you're creative and autonomous, with a genuine passion for technology, we want to hear from you.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 3, and 152,000 USD - 253,000 USD for Level 4.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until September 1, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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