Serbia-Senior Software Engineer - RISC-V Virtualization
SerbiaRISC-VKernel / LinuxPosted Aug 11, 2026
Overview
- Added in 30 days
- 3
- At this company, still open
Skills named in this posting
- C++
- Python
- Boot firmware
- Virtualization
Description
NextSilicon is a swiftly growing unicorn startup that is reimagining high-performance computing. Our pioneering RISC-V and accelerator coprocessor vastly accelerates supercomputers, driving them forward into a new generation. Our new software-defined hardware architecture enables HPC and AI to fulfill its promise of breakthroughs in all advanced research fields.
At NextSilicon, everything we do is guided by three core values:
• Professionalism: We strive for exceptional results through professionalism and unwavering dedication to quality and performance.
• Unity: Collaboration is key to success. That's why we foster a work environment where every employee can feel valued and heard.
• Impact: We're passionate about developing technologies that make a meaningful impact on industries, communities, and individuals worldwide.
We are seeking a highly skilled and experienced Software Engineer to join our team. In this role, you will be responsible for the architecture and implementation of virtualization support for our custom RISC-V implementation, ensuring our hardware-software synergy delivers maximum performance for virtualized workloads.
Requirements
• B.Sc in Electrical Engineering, Computer Science, or equivalent experience.
• 7+ years of experience as a low-level software engineer.
• Deep technical literacy: Ability to digest and implement complex technical specifications, specifically the RISC-V H-extension (Hypervisor).
• Virtualization expertise: Solid understanding of virtualization fundamentals, including nested page-tables, virtualized I/O, and IOMMU logic.
• Strong OS Internals: Proficiency in kernel-level development and memory management.
• Strong, proven coding skills in C and C++.
• Hardware-aware debugging: Ability to root-cause complex integration issues across the stack, distinguishing between software bugs, hardware errata, or spec misinterpretations.
• Familiarity with Python for scripting and internal tooling — an advantage.
• Experience with KVM, OpenSBI, or custom micro-hypervisors — an advantage.
• A proactive, can-do approach and flexible mindset.
• Excellent written and verbal communication skills.
• Ability to work both independently and as part of a collaborative team.
Responsibilities
• Design and implement the virtualization layer and hypervisor support for our custom RISC-V implementation.
• Take ownership of the H-spec implementation, ensuring our software stack is strictly compliant with (or intentionally extends) the RISC-V standard.
• Develop and maintain hypervisor-level software to support guest execution, world-switching, and resource isolation.
• Debug and resolve high-pressure integration issues between our evolving hardware and the software stack (KVM/Hypervisor).
• Implement and optimize memory management strategies, including two-stage translation and I/O virtualization.
• Collaborate closely with hardware teams to validate the H-extension and provide feedback on hardware design from a software perspective.
• Wide system impact through collaboration with software engineers, hardware engineers, and other stakeholders.
Apply on the employer's site
Original posting: comeet.com
RISC-V ecosystem
NextSilicon in the RISC-V ecosystem
RISC-V International: Strategic
Stay tuned...
- NextSilicon is building Arbel, which it presents as its first server-class RISC-V CPU core and "the leading RISC-V core"
- Arbel sits alongside Maverick, its production dataflow accelerator, targeting HPC/AI workloads
- RISC-V is a top-level section of nextsilicon.com, i.e. a core part of the product line
Same employer
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