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Sr Principal Product Validation Engineer

Cadence Design Systems, Inc.

NOIDARTL / HDLVerificationSoC / ASICPosted Sep 21, 2026
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Cadence Design Systems, Inc.
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Skills named in this posting

  • SystemVerilog
  • Verilog
  • VHDL
  • UVM
  • PCIe
  • USB
  • C++
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. • The person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL). • Prior experience in simulation/emulation using these languages. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) with focus towards debugging design/ verification problems using these tools. • Experience in process automation with scripting. • Experience with SystemVerilog, C++, UVM. • Experience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog. • Experience designing and implementing complex functional verification environments is required. • Knowledge of protocols like PCIe, USB3/4, DP an added advantage. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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