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Frontend Engineer

Cadence Design Systems, Inc.

SHANGHAIRTL / HDLPhysical designPosted Sep 21, 2026
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Skills named in this posting

  • Logic synthesis
  • STA
  • Low-power design (UPF)
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. 1.To provide key technical support in digital IC design implementation. 2.To demonstrate strong ability and to be hands-on in RTL-to-GDSII design methodology, including both challenging low power designs. 3.Have real design experience including logic equivalence checking, logic synthesis, 4.Have rich experience for RTL debug, RTL timing and power analysis. 5: Rich experience for Synthesis flow, and be familiar with backend implementation Position Requirements: 1.Master/Bachelor's degree is essential and 3+ years’ experience in IC design, electronic engineering or computer science applications. 2. Eager to learn new technologies, and willing to promote new technologies to customers 3.Requires working knowledge of one or more programming languages, and effective communication and soft skills. 4.Ability to debug all kinds of logic equivalent checking issues with formal tools(LEC, etc). 5.Ability to understand the low power design with UPF, IEEE1801, CPF,etc. 6.Have knowledge or experience in debugging the low power design issue with static check tools(ie. CLP ,etc). 7.Have experience in STA flow. 8.Have knowledge or experience in RTL coding is Plus. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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