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Intern SSG

Cadence Design Systems, Inc.

CORK 01SoC / ASICPosted Sep 21, 2026
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Skills named in this posting

  • Emulation
  • UCIe / chiplets
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Summary Cadence Cork are recruiting key talent across several Universities to join our Internship Programme. If you are passionate about technology and would love to learn and grow in a cross-geographic and multi-cultural organization, developing next-generation software, then Cadence Cork is for you: At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Title: Intern (SSG Business Unit) Location: Cork Reports to: Group Director Job Overview: This Internship will introduce you the basics skills of SoC system level validation and automation of such tasks. You will use Cadence tools such as the Incisive simulator and the Palladium emulator and create, run, debug , and analyse system level tests in pre-silicon environmnts. You will also participate in team meetings and learn firsthand how an industry design team builds chiplets. Role responsibilities: The internship offers the opportunity to contribute to the development of the IC products and get a great insight into the design environment, methodologies and tools of system level validation teams. Job Qualifications: · Bachelors or Masters program in EEE or CS · Interest in finding out more about digital IC design, signal processing (digital and analogue), telecommunications and control theory. We’re doing work that matters. Help us solve what others can’t.

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Original posting: cadence.wd1.myworkdayjobs.com

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RISC-V ecosystem

Cadence Design Systems, Inc. in the RISC-V ecosystem

RISC-V International: Strategic

Cadence is a leading provider of EDA and semiconductor IP.

  • EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
  • Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows

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