Sr Principal Design Engineer- Mixed Signal
CARYRTL / HDLPosted Oct 22, 2026
Overview
- Added in 30 days
- 679
- At this company, still open
Skills named in this posting
- SystemVerilog
- Mixed-signal
- Python
- Perl
At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
We offer amazing opportunities to grow, no matter where you are in your career.
This is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links.
The successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.
Candidate must have a thorough understanding of the following:
• Mixed-signal circuit design fundamentals
• Mixed-signal circuit design and verification flows
• Cadence analog design environment
• Basic signal processing concepts
Familiarity with the following items is a plus:
• Serial link design techniques
• Data converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques
• MATLAB or C to facilitate architecture development
• Hardware description languages such as SystemVerilog or VerilogA for functional model development
• Scripting languages such as Perl or Python for automation
• Silicon validation testing knowledge and experience
Other requirements:
• Excellent verbal and written communication skills
• Ph.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies
The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
Be proud and passionate about the work you do. Together, our One Cadence -- One Team culture drives our success.
We’re doing work that matters. Help us solve what others can’t.
Apply on the employer's site
Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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