Product Engineering Internship, Electronics Hardware Design (Fall 2026)
Burlington, MAPosted Sep 21, 2026
Overview
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At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Job Description
Product Engineering Internship, Electronics Hardware Design (Fall 2026)
This Product Engineering Internship will take place at our Burlington office during the Fall Semester.
Responsibilities:
• As a Product Engineering intern, you will have the chance to contribute to the development of innovative Electronic Design Automation (EDA) software used for designing advanced PCBs.
• Engage with emerging Agentic AI technologies to support and manage PCB design generation.
• Help create Product Requirement Specifications by gathering and analyzing data from technical experts, customers, and colleagues.
• Provide development teams with feedback on layout tool functionality, user experience, and overall use models.
Requirements:
• Currently enrolled as a student pursuing a BSEE or an equivalent degree.
• Experience or coursework in designing, developing, and testing electrical systems.
• Strong focus on digital systems, signal processing, and electronics, with considerable hands-on lab experience.
• Familiarity with electrical and hardware design tools such as Cadence Allegro, Siemens Xpedition, Altium Designer, KiCad.
• Interest in or experience with machine learning and emerging AI methodologies is a plus.
• Must be available to work onsite in Burlington office 40 hours a week. This role is not remote.
• Applicants should be attending local schools to Burlington office.
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Original posting: cadence.wd1.myworkdayjobs.com
RISC-V ecosystem
Cadence Design Systems, Inc. in the RISC-V ecosystem
RISC-V International: Strategic
Cadence is a leading provider of EDA and semiconductor IP.
- EDA vendor active in RISC-V: supported NSITEXE (with Imperas) in developing RISC-V vector processor IP for automotive AI
- Publishes RISC-V ecosystem commentary ("The State of the RISC-V Union", Paul McLellan) and RISC-V verification/emulation flows
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