Senior/Lead DFT CAD and Methodology Engineer
Overview
Skills named in this posting
- DFT
- UCIe / chiplets
- Python
- Perl
We are looking for a highly skilled DFT CAD and Methodology Expert to develop and deploy advanced test methodologies for next-generation data center and AI ASIC. Enhancing the efficiency and quality of our ASIC development and testing procedures. The successful candidate will work within the CAD team to innovate test solutions for complex 2.5D/3DIC, ensuring high quality and yield for advanced packaging technologies.
Key Responsibilities
• Methodology Development: Develop and deploy robust CAD flows for scan insertion, ATPG, pattern simulation, and Memory BIST (MBIST).
• Tool Automation: Create scripts (Python, TCL, Perl) to enhance and automate DFT flows, accelerating simulation runtimes and improving quality of results (QOR).
• EDA Tool Integration: Collaborate with EDA vendors to enhance tools for advanced packaging, including test verification and pattern generation.
• Support & Debug: Support DFT integration teams with CAD flow issues, debug complex issues, and provide technical mentorship.
• 3DIC/2.5D Expertise: Develop and implement testing strategies for chiplets and TSV-based 3D stacks.
Location: Hsinchu, Taipei, Singapore.
#LI-LYNN
Apply on the employer's site
Original posting: careers.mediatek.com
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MediaTek Inc in the RISC-V ecosystem
RISC-V International: Strategic
We make semiconductor technology for #Smartphone, #IoT, #Network as well as TV, Tablet, Blu-ray & many other devices.
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