Senior High Speed SerDes Validation Engineer
US, CA, Santa ClaraPosted Sep 28, 2026
Overview
- Added in 30 days
- 647
- At this company, still open
Skills named in this posting
- Ethernet
- SerDes
- C
- C++
- Python
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI — the next era of computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work, to amplify human imagination and intelligence. Make the choice to join us today.
We are now looking for a Senior Validation Engineer in the DGX Server Product Engineering Team. In this role you will be working with a team of HW/SW engineers to develop and implement complex automated test plans for our industry leading GPU accelerated computing products.
What you will be doing:
• Own validation of products from start to finish including test plan development, automation, design for validation requirements, resource planning, coverage metrics, test execution, bug resolution, and release to production.
• Collaborate with ODMs, component suppliers, and QA teams to ensure no gaps in coverage.
• Coordinate internal and external teams in different times zones.
• Develop system level stress and performance testing strategies using industry leading Deep Learning/AI applications.
• Solve complex system level hardware and software issues on GPU accelerated computing platforms.
What We Need to See:
• Ability to work on site in hardware lab environment 5 days a week
• BSEE or BSCE or equivalent experience
• High speed IO validation
• 6+ years or more of experience in validating and debugging complex systems.
• Developing/running real world workload and factory diagnosis tools
• Outstanding verbal and written communication skills.
• Proficient in collaborating across teams and suppliers to deliver quality products on tight schedules.
• Familiarity with lab instrumentations like Oscilloscopes (Digital Multi Meter)
• High-speed SERDES validation experience (50GBaud/s and above) is a must.
• Strong understanding of DSP-based high-speed SERDES architectures as well as coding experience with programming and scripting languages such as C/C++, JS and Python.
Ways to stand out from the crowd:
• Experience with datacenter products including system management, security, networking, and storage.
• Familiarity with Ethernet and InfiniBand switch architectures is a strong plus.
• Hands-on experience with SERDES performance tuning would be a strong advantage.
• Track record of continuous process improvement with a passion for tools and automation.
• Proven knowledge in Circuit and Waveform analysis.
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 168,000 USD - 264,500 USD for Level 4, and 196,000 USD - 310,500 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until October 2, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
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Original posting: jobs.nvidia.com
RISC-V ecosystem
NVIDIA Corporation in the RISC-V ecosystem
RISC-V International: Premier Board
Founded in 1993, NVIDIA is an AI computing company. The company is headquartered in Santa Clara, California.
- NVIDIA is bringing CUDA platform support to RISC-V, i.e. allowing a RISC-V CPU to host CUDA GPU applications
- Publicly credited the RVA23 profile as the enabler: "We wouldn't have considered porting CUDA to RISC-V without it"
- Active in RISC-V International profile/standards work and a frequent presence in RISC-V ecosystem coverage
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